Method for protecting a semiconductor device with a superconductive line
AssigneeLSI Logic Corporation
InventorsMichael D. Rostoker, Mark Schneider, Nicholas F. Pasch, Abraham Yee, William C. Schneider
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AssigneeLSI Logic Corporation
InventorsMichael D. Rostoker, Mark Schneider, Nicholas F. Pasch, Abraham Yee, William C. Schneider
Estimating the term…
Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g., transistor structures) from over-current or overheating conditions such as those caused by CMOS latch-up. Current density limits and/or thermal limits of superconductors are employed to cause a superconductive trace to become non-superconductive when these limits are exceeded.
A method, of protecting a semiconductor device from current and/or heat overload, comprising:
Method for reducing CMOS latch-up in a semiconductor device, comprising:
Dependencies are inferred from the claim text.