Double dense ferroelectric capacitor cell memory

A semiconductor memory comprising

• means including a ferroelectric capacitor having a non-volatile mechanism storing first data therein and a volatile storing mechanism simultaneously storing second data therein,
• a bit line,
• a plate line,
• a transfer switch connected serially with said ferroelectric capacitor between said bit line and said plate line,
• reference voltage means,
• sensing means having first and second nodes, said bit line line and said reference voltage means being connected to the first and second nodes, respectively, of said sensing means,
• a buffer cell connected to said bit line, and
• means including word line and plate line decoder and driver means coupled to said transfer switch and to said plate line for reading the second data from said ferroelectric capacitor and for storing said second data into said buffer cell and for subsequently reading said second data from said buffer cell and for restoring said second data back into said ferroelectric capacitor without destroying the first data.

A semiconductor memory comprising

• a ferroelectric capacitor including a non-volatile mechanism having first and second states and a volatile storing mechanism,
• means for applying a first voltage to said ferroelectric capacitor to set said ferroelectric capacitor in one of said first and second non-volatile states to store a first binary digit of information in said ferroelectric capacitor and for subsequently applying a second voltage having a significantly smaller magnitude than that of said first voltage insufficient to erase the first binary digit to said ferroelectric capacitor to simultaneously store a second binary digit of information in the volatile storing mechanism of said ferroelectric capacitor,
• a buffer cell,
• means for reading the second binary digit of information stored in said ferroelectric capacitor and for transferring the second binary digit of information to said buffer cell, and means for reading the first binary digit of information stored in said ferroelectric capacitor.

A method of operating a ferroelectric capacitor cell memory for simultaneously storing first and second binary digits of information therein, said memory including a ferroelectric capacitor having a non-volatile mechanism having first and second states and a volatile storing mechanism and a buffer cell, the steps of the method comprising

• applying a first voltage to said ferroelectric capacitor to set said ferroelectric capacitor in one of said first and second non-volatile states to store the first binary digit of information in said ferroelectric capacitor,
• applying a second voltage having a smaller magnitude than that of the first voltage insufficient to erase the first binary digit to said ferroelectric capacitor after storing said first binary digit to simultaneously store a second binary digit of information in the volatile storing mechanism of said ferroelectric capacitor,
• reading the second binary digit of information stored in said ferroelectric capacitor and transferring the second binary digit of information to said buffer cell, and
• reading the first binary digit of information stored in said ferroelectric capacitor after storing the second binary digit of information in said buffer cell.

A method of operating a ferroelectric capacitor cell memory for simultaneously storing first and second binary digits of information therein, said memory including a ferroelectric capacitor having first and second polarization states and a volatile storage mechanism and a buffer cell, the steps of the method comprising

• applying a first voltage to said ferroelectric capacitor to set the ferroelectric capacitor in one of the first and second polarization states to store the first binary digit of information in said ferroelectric capacitor,
• applying a second voltage having a significantly smaller magnitude than that of the first voltage insufficient to erase the first binary digit to said ferroelectric capacitor after storing the first binary digit to simultaneously store the second binary digit of information in the volatile storage mechanism of said ferroelectric capacitor,
• reading the second binary digit of information stored in said ferroelectric capacitor and transferring the second binary digit of information to said buffer cell, and
• reading the first binary digit of information stored in the ferroelectric capacitor after storing the second binary digit in said buffer cell.

A semiconductor memory comprising

• means including a multi-level data storage device having a non-volatile mechanism with first and second states for storing a first binary digit of information and a volatile storing mechanism for simultaneously storing a second binary digit of information,
• a buffer cell,
• a bit line connected to said multi-level data storage device and to said buffer cell,
• sensing means connected to said bit line, and
• means coupled to said sensing means, said multi-level data storage device and said buffer cell for transferring said second binary digit of information from said multi-level data storage device to said buffer cell through said bit line without destroying the first binary digit of information remaining in said multi-level data storage device.