US 5,638,534 AGranted

Memory controller which executes read and write commands out of order

AssigneeSamsung Electronics Co., Ltd.

InventorL. Randall Mote, Jr.

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Abstract

A memory subsystem includes a posted write buffer for dynamic random access memories (DRAMs). The posted write buffer includes read around logic to enable read accesses to be processed in advance of posted writes. Data are transferred from the posted write buffer to the DRAMs on a general first-in/first out basis; however, in order to take advantage of page mode operation, posted writes having the same row address as a current memory access are given priority over other posted writes such that the posted writes may be written out of order. In addition, comparisons are made between addresses of incoming read accesses and addresses of posted writes in order to expedite the transfer of posted writes having the same row addresses to memory in order to service the incoming read accesses on a timely basis. An improved write access buffer permits posted writes to be transferred to the DRAMs out of order without losing track of the skipped posted writes.

Claims6

Dependent claims

A memory controller which controls a dynamic random access memory (DRAM) system which receives a plurality of write access requests having respective addresses and associated data to be written to said DRAM system at said addresses, each of said write addresses having a row address portion and a column address portion, said memory controller comprising:

a buffer having a plurality of locations which temporarily store said write addresses and associated data for each of said write access requests until said data can be written to said DRAM system, said stored addresses and data being maintained in said buffer in an order corresponding to an order in which said write access requests are received;
and
an access sequence control circuit which selects address and data associated with one of said plurality of write access requests as a next access to said DRAM system, said access sequence control circuit comprising:
a comparator which compares said row address portion of each of said stored addresses with said row address portion of a current access and identifies write access requests having respective row address portions identical to said row address portion of said current access;
and
an access selector circuit responsive to said comparator which selects one of said identified write access requests as a next access to said DRAM system before selecting a non-identified write access request having a row address portion different from said row address portion of said current access, said selection of said one of said identified write access requests being made even if said non-identified write access request was made prior to said identified write access request.

3 more elements

A method for controlling access to a dynamic random access memory (DRAM) system having a plurality of memory storage locations, wherein said DRAM system is accessed by applying a row address to said DRAM system and then applying a column address to said DRAM system, said DRAM system providing access to a plurality of locations having the same row address by changing only the column address between accesses, said method comprising the steps of:

storing an address and associated data for each of a plurality of write access requests in a buffer, each address of said plurality of access requests comprising a row address portion and a column address portion, each address and associated data stored in an order in which said memory controller receives said access requests;
performing a first access to said DRAM system at a first row address and a first column address;
comparing said first row address portion with said row address portion of each access request stored in said buffer;
when at least one access request in said buffer has a row address portion identical to said row address portion of said first access, selecting as a second access to said DRAM system an earliest received access request of said at least one access request having a row address portion identical to said row address portion of said first access, said at least one access request having an identical row address portion being selected before earlier access requests having non-identical row address portions;
and
when no access request in said buffer has a row address portion identical to said row address portion of said first access, selecting an earliest received access request in said buffer as said second access.

3 more elements

Dependencies are inferred from the claim text.