Processor capable of executing programs that contain RISC and CISC instructions

A computer system comprising;

• a bus;
• an external memory coupled to said bus;
• a microprocessor coupled to said external memory and said bus, said microprocessor including:
• first and second register files;
• an instruction cache that stores first and second instructions of a program;
• a first decoder coupled to said instruction cache that decodes said first instruction;
• a second decoder coupled to said instruction cache that decodes said second instruction;
• a multiplexor having inputs coupled to said first and second decoders, and an output;
• an execution unit coupled to said output of said multiplexor that executes said first and second instructions, with a first result of said first instruction being written to said first register file, and a second result of said second instruction being written to said second register file.

In a processor having first and second instruction set operating modes, a method for executing a program that contains instructions of first and second instruction sets, said method comprising steps of:

• (a) executing a first instruction of said first instruction set while said processor is in said first instruction set operating mode;
• (b) receiving a first interruption indication;
• (c) servicing said first interruption indication while said processor is in said second instruction set operating mode;
• (d) returning to said first instruction set operating mode.

In a processor, a method for executing a program that contains RISC and CISC instructions comprising steps of:

• (a) executing a first instruction in said program, said first instruction being one of said CISC instructions;
• (b) executing a switch instruction, the switch instruction including a value that indicates a location of a next instruction in said program;
• and
• (c) executing said next instruction in said program, said next instruction being one of said RISC instructions.