US 5,638,518 AGranted

Node loop core for implementing transmission protocol in fibre channel

AssigneeLSI Logic Corporation

InventorSrinivasa R. Malladi

Life of this patent

Estimating the term…

Loading patent…

Abstract

Disclosed is a node loop port core for use in a Fibre Channel high speed data system for implementing transmission protocol and loop arbitration. The node loop core converts incoming data from 10 bit format to 8 bit format, checks frame CRC, parses frames, and steers the results to any one of a number of buffers. The buffers function as loading areas for incoming frames and are not part of NL core. In transmit operation, the node loop core chooses a loaded buffer to service, assembles frames, generates and adds CRC to frames, encodes the result from 8 bit to 10 bit format and then transfers the results. All control functions associated with primitive signals and sequences are handled by the node loop core. The core follows established Fibre Channel arbitration rules and recognizes all necessary primitive signals and primitive sequences for proper operation of the arbitrated loop.

Claims6

Dependent claims

A node loop port core for use in a high speed data system such as Fibre Channel for encoding, decoding and error control of transmitted data, said node loop port core comprising:

a decode unit for receiving and decoding data including converting data width with error checking and constructing parity protected words from halfwords and bytes,
an encode unit for encoding data for transmission including converting data width and generating encoded halfwords or bytes after checking parity,
a receive unit coupled with said decode unit for forwarding data to a host interface after frame parsing, frame steering and error checking,
a transmit unit coupled with said encode unit for frame construction, CRC generation, Fibre Channel primitive signal and sequence generation, and
an arbitrated loop coupled to said decode unit, said encode unit, said receive unit, and said transmit unit, said arbitrated loop unit performing all arbitration functions including recognition of primitive signals and sequences pertinent to said loop, said arbitrated loop including:
a loop state machine for performing loop initialization protocol, loop arbitration and loop fairness in accordance with Fibre Channel specifications,
a first multiplexer controlled by said loop state machine for receiving and transmitting decoded data from said decode unit,
a second multiplexer controlled by said loop state machine for receiving and transmitting data from said transmit unit for port to port communication, and
a loop buffer connected with said loop state machine for receiving and retiming received words.

6 more elements

A node loop port core for use in a high speed data system such as Fibre Channel for encoding, decoding and error control of transmitted data, said node loop port core comprising:

a) a decode unit for receiving and decoding data including converting data width with error checking and constricting parity protected words from halfwords and bytes, said decode unit including:
a 20 bit input for use when a 20 bit mode is enabled,
a 10 bit input for use when a 10 bit mode is enabled,
a 10 bit decoder coupled to said inputs and including two parallel 10 bit to 8 bit decoders with error checking,
a parity generator coupled to said decoder for receiving decoded data and generating and appending odd parity,
a word assembler coupled to said parity generator for assembling 32 bit parity protected data for said arbitrated loop, and
a receive word controller for receiving control signals and generating control signals and controlling operations in said decode unit;
b) an encode unit for encoding data for transmission including converting data width and generating encoded half-words or bytes after checking parity, said encode unit including:
a 20 bit output for use when a 20 bit mode is enabled,
a 10 bit output for use when a 10 bit mode is enabled,
an 8 bit encoder coupled to said outputs and including two parallel 8 bit to 10 bit encoders,
a parity checker coupled to said encoder and checking off parity and stripping a parity bit,
a word disassembler coupled to said parity checker for disassembling 32 bit parity protected data into 16 bit parity protected data for said parity checker and encoder, and
a transmit word controller for receiving control signals and generating status signals and controlling operations in said encode unit;
c) a receive unit coupled with said decode unit for forwarding data to a host interface after frame parsing, frame slicing, error checking, said receive unit including:
a detect ordered set unit for receiving decoded words from said decode unit and detecting primitive signals, primitive sequences, and frame delimiters,
a receive pipeline for recovery decoded words from said decode unit,
a CRC unit for generating CRC bits for incoming frames from said receive pipeline and checking for correct CRC bits,
a multiplexer for recovering data from said receive pipeline for transmission downstream,
a steering control unit for providing logic signals for frame parsing and steering,
a frame interface formats (FIF) converter for converting Fibre Channel Standard format to FIF format,
a frame control unit for providing frame parsing information for use in custom steering,
a base address register for providing a base address for vectoring frames to a memory, and
a receive control unit coupled to and controlling all other units of said receive unit, and providing all required status signals to downstream logic;
d) a transmit unit coupled with said encode unit for frame construction, CRC generation, Fibre Channel primitive signal and sequence generation, said transmit unit including:
a header multiplexer for multiplexing frame headers from multiple sources,
a frame data multiplexer unit connected to said header multiplexer and receiving payload and link inputs and multiplexing data and headers of frames,
a CRC generate unit connected to receive outputs from said frame data multiplexer and generating a CRC for frames,
an output multiplexer connected to receive outputs from said CRC generate unit and including data paths for header and data, for start of frame SOF and end of frame EOF delimiters, and CRC, said output multiplexer presenting transmission words to said encoder through said arbitrated loop,
a hardware sequencing parameters and registers unit for providing necessary parameters for hardware managed sequences to said header multiplexer,
a unit for performing primitive signal, sequence, and delimiter generation,
a flow control unit for hardware managed flow control and responsive to a R.sub.-- RDY (receive unit ready) signals from a remote link receiver, and
a transmit control unit interconnected with and controlling all units in a transmit operation including single frames from said frame data multiplexer unit, sequences of frames in a hardware managed sequencing, idles and primitive sequences, buffer to buffer flow control, frame delimiter generation, offset generation, and CRC generation and transmission for end of frame transmission;
e) an arbitrated loop coupled to said decode unit, said encode unit, said receive unit, and said transmit unit, said arbitrated loop unit performing all arbitration functions including recognition of primitive signals and sequences pertinent to said loop, said arbitrated loop including:
a loop state machine for performing loop initialization protocol, loop arbitration and loop fairness in accordance with Fibre Channel specifications,
a first multiplexer controlled by said loop state machine for receiving and transmitting decoded data from said decode unit,
a second multiplexer controlled by said loop state machine for receiving and transmitting data from said transmit unit for port to port communication, and
a loop buffer connected with said loop state machine for receiving all retiming received words.

35 more elements

Dependencies are inferred from the claim text.