Data communication system
AssigneeKabushiki Kaisha Toshiba
InventorsKatsuhiko Hayashi, Toru Tateishi, Katsumi Murano, Takayasu Aoki, Hiroaki Sato
Life of this patent
Estimating the term…
Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorsKatsuhiko Hayashi, Toru Tateishi, Katsumi Murano, Takayasu Aoki, Hiroaki Sato
Estimating the term…
In order to combine an ARQ system and an FEC system, an error correction code is inserted between an error detection code for a variable-length ARQ frame and a frame boundary flag pattern. Information to be transmitted is divided into blocks having a suitable length by a block divider in accordance with a line quality judged by a line quality judger, and then subjected to a framing operation by an information frame preparer. The information subjected to the framing operation is attached with a CRC code by a CRC code generation/application circuit, subjected by a zero insertion circuit to an insertion of a suitable number of zero bits therein to provide a distinguished frame boundary with a flag, and the transmitted.
A data communication system for transmitting/receiving digital information via a duplex communication line comprising:
A data communication system comprising:
A data communication system comprising:
A data communication system comprising:
Dependencies are inferred from the claim text.