Integrated circuit I/O using a high performance bus interface
AssigneeRambus Inc.
InventorsMichael Farmwald, Mark Horowitz
Life of this patent
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Abstract
The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.
Claims13
A memory device addressable over a range of addresses, the memory device comprising:
- plurality of independently addressable memory sections, wherein each of the memory sections is assigned a portion of the range of addresses, each of the memory sections comprising an array of memory cells connected in rows and columns;
- and
- a plurality of address registers coupled to the plurality of memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections, and wherein at least one of the plurality of address registers specifies that a zero portion of the range of addresses is assigned to at least one of the plurality of memory sections if the at least one of the plurality of memory sections is defective.
A memory system addressable over a range of address, the memory system comprising:
- a first memory device;
- a second memory device;
- wherein the first and second memory devices each comprise:
- a plurality of independently addressable memory sections, wherein each of the memory sections corresponds to a portion of the range of addresses;
- and
- a plurality of address registers coupled to the plurality of memory sections, each address register storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections, wherein at least one of the plurality of address registers in the first or second memory device specifies that a zero portion of the range of addresses is assigned to at least one of the plurality of memory sections in the first or second memory device if the at least one of the plurality of memory sections is defective.
Dependencies are inferred from the claim text.