Hierarchical DRAM array with grouped I/O lines and high speed sensing circuit

A random access memory comprising:

• a plurality of subarrays arranged into rows and columns, each subarray including:
• a plurality of bit line pairs having a plurality of memory cells connected thereto;
• a plurality of first sense amplifiers, at least one for each bit line pair, connected to said bit line pairs, each of said sense amplifiers having true and complement output terminals providing true and complement output signals;
• a plurality of pass transistor pairs, one of said pass transistor pairs for each of said plurality of first sense amplifiers, each of said pass transistor pairs having a true pass transistor and a complement pass transistor, each of said true and complement pass transistors having a control terminal connected to receive a sense amplifier select signal, the true pass transistor having a first current handling terminal connected to the true output terminal of one of said first sense amplifiers and having a second current handling terminal, the complement pass transistor having a first current handling terminal connected to the complement output terminal of said one of said first sense amplifiers and having a second current handling terminal;
• a sub I/O bus having a true lead connected to the second current handling terminals of the true pass transistors and having a complement lead connected to the second current handling terminals of the complement pass transistors;
• a local I/O bus comprising true and complement leads, said local I/O bus running parallel to said bit line pairs, said true lead of said local I/O bus being connected to said true lead of said sub I/O bus via a true bus interconnect transistor, said true bus interconnect transistor having a control terminal connected to receive a subarray write selection signal, and said complement lead of said local I/O bus being connected to said complement lead of said sub I/O bus via a complement bus interconnect transistor, said complement bus interconnect transistor having a control terminal connected to receive said subarray write selection signal;
• and
• a second sense amplifier having a first transistor, said first transistor having a control terminal connected to said true lead of said sub I/O bus, a first current handling terminal connected to said complement lead of said local I/O bus and a second current handling terminal, said second sense amplifier having a second transistor, said second transistor having a control terminal connected to said complement lead of said sub I/O bus, a first current handling terminal connected to said true lead of said local I/O bus and a second current handling terminal connected to said second current handling terminal of said first transistor, said second sense amplifier having a third transistor, said third transistor having a control terminal connected to receive a subarray read select signal, a first current handling terminal connected to the second current handling terminals of said first and second transistors, and a second current handling terminal, said second sense amplifier having a fourth transistor, said fourth transistor having a control terminal connected to receive a section select signal, a first current handling terminal connected to said second current handling terminal of said third transistor and a second current handling terminal connected to a reference potential.