Wireless radio frequency power semiconductor devices using high density interconnect

A power device component package, comprising:

• an electrically conductive drain lead;
• a power device component having component pads, said component having an electrically conductive backside supported by and electrically coupled to said drain lead;
• a dielectric layer overlying at least a portion of said component, said dielectric layer having a plurality of vias therein aligned with predetermined ones of said component pads;
• a pattern of electrical conductors extending through selected ones of said vias, a first portion of said pattern coupling selected ones of said component pads, and a second portion of said pattern contacting at least one other of said component pads;
• an electrically conductive source lead;
• a layer of solder coupling said source lead to said first portion of said pattern of electrical conductors;
• an electrically conductive gate lead, each of said drain, source, and gate leads having a thickness sufficient to form a high current contact;
• and
• a layer of solder coupling said gate lead to said second portion of said pattern of electrical conductors.

A power device component package, comprising:

• a substrate comprising insulative material;
• a drain lead, a source lead, and a gate lead, each of said leads being supported by said substrate and comprising an electrically conductive material having a thickness sufficient to form a high current contact;
• a power device component having component pads, said component having an electrically conductive backside supported by and electrically coupled to said drain lead;
• a dielectric layer overlying at least portions of said component and said source lead, said dielectric layer having a plurality of vias therein aligned with predetermined ones of said component pads and at least a predetermined portion of said source lead;
• and
• a first pattern of electrical conductors extending through selected ones of said vias and coupling selected ones of said component pads to said source lead;
• a middle pattern of electrical conductors extending through at least one other of said vias and contacting at least one other of said component pads;
• an additional dielectric layer over at least a portion of said gate lead, at least a portion of said dielectric layer, and at least a portion of said middle pattern of electrical conductors, said additional dielectric layer and having at least one additional via therein aligned with a predetermined portion of said middle pattern and at least one other additional via therein aligned with a predetermined portion of said gate lead;
• and
• a second pattern of electrical conductors extending through said at least one additional via and said at least one other additional via to couple said gate lead and said middle pattern.

A power device component package, comprising:

• a substrate comprising insulative material;
• a drain lead, a source lead, and a gate lead, each of said leads being supported by said substrate and comprising an electrically conductive material having a thickness sufficient to form a high current contact;
• a power device component having component pads, said component having an electrically conductive backside supported by and electrically coupled to said drain lead;
• a dielectric layer overlying at least portions of said component and said source lead, said dielectric layer having a plurality of vias therein aligned with predetermined ones of said component pads and at least a predetermined portion of said source lead;
• and
• a first pattern of electrical conductors extending through selected ones of said vias and coupling selected ones of said component pads to said source lead;
• an additional dielectric layer over at least a portion of said gate lead and at least a portion of said dielectric layer, said additional dielectric layer and said dielectric layer having at least one additional via extending through each of said dielectric layers to another of said chip pads and at least one other additional via therein aligned with a predetermined portion of said gate lead;
• and
• a second pattern of electrical conducters extending through said at least one additional via and said at least one other additional via and coupling said another of said chip pads to said gate lead.

A package of power device components, comprising:

• a substrate comprising insulative material;
• first and second electrically conductive drain leads supported by said substrate;
• an electrically conductive source lead supported by said substrate;
• first and second electrically conductive gate leads supported by said substrate, each of said drain, source, and gate leads having a thickness sufficient to form a high current contact;
• a first power device component having component pads and having an electrically conductive backside supported by and electrically coupled to said first electrically conductive drain lead;
• a second power device component having component pads and having an electrically conductive backside supported by and electrically coupled to said second electrically conductive drain lead;
• a dielectric layer overlying at least a portion of said first and second components and at least portions of said source lead, said first drain lead, and said first and second gate leads, said dielectric layer having a plurality of vias therein aligned with predetermined ones of said component pads and predetermined portions of said source lead, said first drain lead, and said first and second gate leads;
• and
• a pattern of electrical conductors extending through said vias and coupling selected component pads to respective selected ones of said first drain lead, said first and second gate leads, and said source lead.