Nonvolatile semiconductor memory device with dual insulation layers between adjacent gate structures

Abstract

A non-volatile semiconductor memory, called EPROM has a plurality of memory cells arrayed in a matrix and each having a laminate gate structure including a part of a strip control gate and a separate floating gate. A plurality of erasing gates is disposed in one of each two of spaces formed between two adjacent gate structures. Other of the each two of the spaces is filled with a laminate including a silicon nitride film and a silicon oxide film overlying the silicon nitride film. The erasing gates and the laminates are arranged alternately, so that the laminates do not cover the erasing gates. Difference in level between the memory cell section and the peripheral section is reduced to thereby prevent breakage of interconnects overlying the erasing gates. Etching of the substrate surface can be avoided to thereby obtain an improvement in the yield of the memory device.

Dependencies are inferred from the claim text.