Method and apparatus for performing operations based upon the addresses of microinstructions

A microprocessor capable of generating special bus cycles, said microprocessor comprising:

• a storage means for storing microinstructions, said microinstructions comprising a first microinstruction and a second microinstruction;
• a means for reading a microinstruction from the storage means;
• a means for generating an address corresponding to a requested operation to be performed in response to said microinstruction, wherein if said microinstruction is a first microinstruction, said means for generating an address generates an address at which the microinstruction is to be performed, and if said microinstruction is a second microinstruction, said means for generating an address generates an address identifying an operation to be performed by an unit of said microprocessor;
• and
• a means for transmitting said microinstruction having said address to a unit of said microprocessor, such that if said microinstruction is the second microinstruction, said unit determines whether said microinstruction is to be executed based on said address, wherein if said microinstruction is not to be executed, said microinstruction is ignored, and if said microinstruction is to be executed said unit performs the requested operation specified by said address.

A computer system comprising:

• a bus;
• a main memory coupled to said bus for storing digital data;
• and
• a microprocessor coupled to said bus for processing said digital data, said microprocessor comprising:
• a local memory for storing microinstructions, said microinstructions comprising a first microinstruction and a second microinstruction;
• a plurality of units including:
• an instruction fetch unit for reading a microinstruction from the local memory;
• an address generation unit coupled to said instruction fetch unit, wherein if said microinstruction is a first microinstruction said address generation unit generating an address at which the microinstruction is to be performed, and if said microinstruction is a second microinstruction said address generation unit generating an operation address identifying an operation to be performed by a unit of the plurality of Units of said microprocessor;
• and
• a circuit coupled to said instruction fetch unit for conveying said microinstruction having said address over a bus to the plurality of units of said microprocessor, wherein if said microinstruction is the second microinstruction each unit of the plurality of units determines whether said operation is to be executed based on said address of the second microinstruction, wherein if said operation is not to be executed by a unit of the plurality of units, said operation is ignored by the unit, and if said operation is to be executed by a unit of the plurality of units, said unit performs the operation specified by said operation address.

In a microprocessor comprising a plurality of units, a method for performing operations comprising the steps of:

• (a) reading a microinstruction from a memory, said microinstruction comprising an address field;
• (b) generating an operation address to be placed in the address field of the microinstruction read from memory, said operation address indentifying an operation to be performed by a unit of a plurality of units;
• (c) transmitting the microinstruction comprising the operation address to a first unit of the plurality of units;
• (d) upon receipt of the microinstruction, said first unit examining the operation address;
• (e) if the first unit is to perform the operation identified by the operation address, said first unit performing the operation;
• (f) if the first unit is not to perform the operation identified by the operation address, said first unit transmitting the microinstruction to a next unit of the plurality of units;
• (g) performing steps (d), (e) and (f) until the operation specified by the operation address is performed.