System and method for interfacing risc busses to peripheral circuits using another template of busses in a data communication adapter
AssigneeInternational Business Machines Corporation
InventorsPatrick Sicsic, Alain Benayoun, Jean-Francois LePennec, Patrick Michel
Life of this patent
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Abstract
A conversion cache circuit, interfacing RISC busses to CISC peripheral circuits, provides master/slave Write and Read operations in a shared memory (130) and in the internal registers of the processor of said peripheral circuits (210). It enables RISC processor to Write and Read in the internal registers of the 8-bit processor in a salve operation while the 32-bit processor may perform the Write or Read operations to the shared memory through the conversion cache circuit in a master mode. The 32-bit processor may have access directly to the memory through its own direct access memory mechanism.
Claims9
A conversion circuit (140) for interfacing a RISC processor (100) using a RISC interface bus to peripheral circuit (200, 210) using a CISC interface bus 4 and connected to a network, said RISC interface bus comprising a bidirectional multiplexed address/data 6 bus (600), RISC control lines (leads 101 to 108) and operating at the frequency defined by a first oscillator (110), said CISC interface bus comprising separated data bus (660) and address bus (650), control lines and operating at a second frequency defined by a second oscillator (340) running slower than the first oscillator;
- said conversion circuit (140) and said RISC processor (100) being connected by said RISC interface bus to a memory storage (130) through a memory controller (120);
- said conversion circuit (140) being characterized in that it comprises:
- first means for receiving addresses and data on said bidirectional multiplexed bus (600) from the RISC processor (100) and from said memory controller (120) to transmit separately on said CISC data bus (660) and address bus (650) to the peripheral circuit (200, 210), in accordance with the CISC timing diagrams and whereby said RISC processor (100) is allowed to have access for read or write operations into internal registers of said peripheral circuit (210);
- and
- second means for receiving addresses and data on said address CISC bus (650) and data on said data CISC bus (660) from the peripheral circuit (200, 210) to transmit on said bidirectional multiplexed RISC bus (600) to the RISC processor (100) and to the memory storage (130) through the memory controller (120), in accordance with the RISC timing diagrams and whereby said peripheral circuit (200) is allowed to have access for read or write operations into the memory storage (130).
A conversion method to be used in a conversion circuit (140) for interfacing a RISC processor (100) using a RISC interface bus to peripheral circuit (200, 210) using a CISC interface bus and connected to a network, said RISC interface bus comprising a bidirectional multiplexed address/data bus (600), RISC control lines (leads 101 to 108) and operating at the frequency defined by a first oscillator (110), said CISC interface bus comprising separated data bus (660) and address bus (650), control lines and operating at a second frequency defined by a second oscillator (340) running slower than the first oscillator;
- said conversion circuit (140) and said RISC processor (100) being connected by said RISC interface bus to a memory storage (130) through a memory controller (120);
- and said conversion circuit (140) comprising first means for receiving addresses and data on said bidirectional multiplexed bus (600) from the RISC processor (100) and from said memory controller (120) to transmit them separately on said CISC data bus (660) and address bus (650) to the peripheral circuit (200, 210), respecting the CISC timing diagrams and whereby said RISC processor (100) is allowed to have access for read or write operations into internal registers of said peripheral circuit (210);
- said conversion method characterized in that it comprises the steps of:
- activating a write/read control signal RS.sub.-- W/R (lead 108) from the RISC processor to indicate whether a write or a read operation is to be performed into the internal registers of said peripheral circuit;
- activating a first control signal RS.sub.-- ADS (lead 104) and a second control signal RS.sub.-- BLAST (lead 105) from said RISC processor (100) to transmit to a first control logic (640) generating therefrom a third control signal AS.sub.-- EN for enabling the read or write operations into said internal registers;
- receiving an address from the RISC processor on a first latch (610) responsive to said third control signal AS.sub.-- EN for transmitting said address to an address decode (630) and to a first buffer (620);
- wherein both the address decode circuit and the first buffer are responsive to a fourth control signal RS.sub.-- HLDA (lead 106) deactivated by the RISC processor when it wishes to access the internal registers for Write/Read operations;
- and wherein said address decode circuit is also responsive to said third control signal AS.sub.-- EN to select which of the internal registers the RISC processor wishes to access by providing a chip select control signal IO.sub.-- CS to said peripheral circuit (210);
- generating an activation signal OE.sub.-- D.sub.-- IO from a second control logic circuit (500) responsive to said write/read control signal RS.sub.-- W/R (lead 108) from RISC processor and to said chip select control signal IO.sub.-- CS;
- receiving the data transmitted from the RISC processor to a second buffer (410);
- said second buffer being responsive to said activation signal OE.sub.-- D.sub.-- IO for transmitting said data to the peripheral circuit (210);
- generating a ready signal IO.sub.-- RDY from a first state machine (520) responsive to said chip select signal IO.sub.-- CS;
- generating a fifth control signal IO.sub.-- WR from a third control logic circuit (510) responsive to said ready signal IO.sub.-- RDY and said chip select signal IO.sub.-- CS to the peripheral circuit (210) informing that the data are ready to be written into the internal registers;
- generating a sixth control signal IO.sub.-- RD from an OR gate (540) responsive to the second control signal RS.sub.-- BLAST (lead 105) and the write/read control signal RS.sub.-- W/R (lead 108) of the RISC processor to said peripheral circuit (210) informing that the data are ready to be read from the internal registers;
- transmitting the data output from the selected internal registers of said peripheral circuit on said bus (660) to a third buffer (420) which therefrom transmits said data on said bidirectional multiplexed address/data RISC bus (600);
- and
- generating a signal from a fourth buffer (530) responsive to said chip select signal IO.sub.-- CS and to said ready signal IO.sub.-- RDY to the RISC processor to inform that the Write/Read operation has been completed.
Dependencies are inferred from the claim text.