US 5,636,365 AGranted

Hierarchical buffer memories for selectively controlling data coherence including coherence control request means

AssigneeNEC Corporation

InventorTakahiro Tanioka

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Abstract

A buffer-memory coherence control mechanism for a data processing system includes a coherence control identification device. For each entry of a second buffer memory to which a plurality of first buffer memories is connected, a control bit for coherence control is stored in a control bit table. The control bit table is provided with 1 bit corresponding to each first buffer memory and indicates which first buffer memory shares a block corresponding to the second buffer memory. When coherence control between the first buffer memories is needed, a coherence control request is issued according to the content of the control bit table only to a specified first buffer memory. In addition, even if a block was cast out of the first buffer memory, the control bit table would not be updated.

Claims23

Dependent claims

A hierarchical buffer memory for a data processing system, comprising a plurality of first buffer memories connected to processors and at least one second buffer memory connected to main storage, wherein said second buffer memory comprises:

a coherence control identification means for identifying a data region having a possibility of being included in said first buffer memories;
and
a coherence control request means for, when issuing a coherence control request of a certain data region to said first buffer memories, issuing said coherence control request to only a first buffer memory identified as having a possibility of including said data region by said coherence control identification means,
wherein said coherence control request means prevents issuance of coherence control requests to said first buffer memories other than said first buffer memory identified by said coherence control identification means, such that a frequency of coherence control requests received by each of said plurality of said first buffer memories is minimized.

1 more element

A buffer memory controller for a hierarchical buffer memory, said hierarchical buffer memory including a plurality of first buffer memories and a second buffer memory, said second buffer memory storing a plurality of data blocks, said controller comprising:

a memory for storing a plurality of data items each corresponding to one of said first buffer memories, each of said data items indicating which one or ones of said first buffer memories have an access history to a corresponding data block;
and
a first circuit for issuing a block clear request to clear one of said data blocks referring to contents of said memory, said first circuit issuing said block clear request to one or ones of said first buffer memories which have an access history to the data block to be cleared,
wherein said first circuit prevents issuance of requests to said first buffer memories other than to said one or ones of said first buffer memory identified by said memory, such that a frequency of requests received by each of said plurality of said first buffer memories is minimized.

1 more element

Dependencies are inferred from the claim text.