Programmable high watermark in stack frame cache using second region as a storage if first region is full and an event having a predetermined minimum priority
AssigneeIntel Corporation
InventorsJames A. Stone, Andre E. Wolper
Life of this patent
Estimating the term…
Abstract
A programmable high watermark for a stack frame cache for eliminating frame spills initiated by certain critical events. A stack frame cache in a microprocessor is divided into two regions. The second region in the stack frame cache is reserved for context switches initiated by high priority events. Low priority events will result in a frame spill when the first region of the stack frame cache is filled. A high priority event will utilize the second region of the stack frame cache for a context switch if the first region is filled, thus eliminating the need for a reference to off-chip main memory.
Claims20
A data processing unit for use in a system having a memory remote from said data processing unit, said data processing unit comprising:
- a plurality of local registers for use by said data processing unit during an executing procedure;
- a stack frame cache coupled to said plurality of local registers for storing a plurality of frames of local register sets, said stack frame cache storing contents of said plurality of local registers upon a context switch;
- high watermark control logic coupled to said stack frame cache, wherein said high watermark control logic determines a first and second region of said stack frame cache, the second region of said stack frame cache available for use if said first region of said stack frame cache is full and a context switch is generated by an event having at least a predetermined minimum priority.
A computer system comprising:
- an input/output (I/O) means for providing a communicating interface;
- a memory means coupled to the I/O means for storing instructions and computer data;
- data input means coupled to the I/O means for providing data input and data output to interface the computer system with a computer user;
- and
- microprocessor means coupled to the I/O means for executing instructions and processing computer data, the microprocessor means including:
- a plurality of local registers for use by said microprocessor during an executing procedure;
- a stack frame cache coupled to said plurality of local registers for storing a plurality of frames of local register sets, said stack frame cache storing the contents of said plurality of local registers upon a context switch;
- and
- high watermark control logic coupled to said stack frame cache, wherein said high watermark control logic determines a first and second region of said stack frame cache, the second region of said stack frame cache available for use if said first region of said stack frame cache is full and a context switch is generated by an event having at least a predetermined minimum priority.
A method of operating a data processing system having a plurality of local registers and a stack frame cache comprising the steps of:
- setting a high watermark value for said stack frame cache, wherein said high watermark value determines a first and second region of frames in said stack frame cache;
- upon a context switch initiated by a procedure having a priority below a predetermined threshold:
- if an empty frame exists in said first region, writing contents of said plurality of local registers to a frame in said first region of said stack frame cache;
- if all frames in said first region are filled, saving the oldest frame in said stack frame cache to an external memory and writing the contents of said plurality of local registers to said frame in said first region of stack frame cache;
- and
- proceeding with executing said procedure having said priority below said predetermined threshold;
- upon a context switch initiated by a procedure having a priority equal to or greater than said predetermined threshold:
- if an empty frame exists in said first region, writing contents of said plurality of local registers to a frame in said first region of said stack frame cache;
- if all frames in said first region are filled, writing contents of said plurality of local registers to a frame in said second region of stack frame cache without initiating a frame spill to external memory;
- and
- proceeding with executing said procedure.
Dependencies are inferred from the claim text.