Performance of an operation on whole word operands and on operations in parallel on sub-word operands in a single processor

A multiplier which multiplies multiplicands, the multiplier implementing both whole word multiplication of whole word multiplicands and implementing parallel multiplication of sub-word multiplicands, the multiplier comprising:

• partial product generation means for generating partial products from the multiplicands;
• partial product sum circuitry, coupled to the partial product generation means, for summing the partial products to produce a result;
• selection means for selecting one of whole word multiplication and parallel multiplication of sub-word multiplicands;
• and,
• partial product selection means, coupled to the partial product generation means and to the selection means, for in response to the selection means selecting parallel multiplication of sub-word multiplicands forcing selected partial products to have a new value, thereby implementing parallel multiplication of sub-word multiplicands.

A method for performing multiplication of multiplicands, the method performing both multiplication of whole word multiplicands and parallel multiplication of sub-word multiplicands, using a single hardware multiplier, the method comprising the steps of:

• (a) generating partial products from the multiplicands;
• (b) in response to a selection to perform parallel multiplication of sub-word multiplicands, forcing selected partial products to have a new value;
• and,
• (c) summing the partial products to produce a result, the summing performed using partial product sum circuitry, when in step (b) the selected partial products are forced to have new values, using the new values when summing the partial products to produce the result.

A processing system comprising:

• an arithmetic logic unit which performs parallel addition and parallel subtraction, the arithmetic logic unit including:
• first partition circuitry which performs an arithmetic operation on a first set of bits from a plurality of operands to produce first results, the first partition circuitry performing the arithmetic operation on low order bits of the plurality of operands,
• second partition circuitry, having an identical logic structure as the first partition circuitry, which performs the arithmetic operation on a second set of bits from the plurality of operands to produce second results, the second partition circuitry performing the arithmetic operation on high order bits of the plurality of operands, and
• first selection means, coupled between the first partition circuitry and the second partition circuitry, for allowing data to propagate from the first partition circuitry to the second partition circuitry and for preventing data from propagating from the first partition circuitry to the second partition circuitry;
• and,
• a preshifter coupled to an input of the arithmetic logic unit, for preshifting a subset of the first set of bits and for preshifting a subset of the second set of bits the second set of bits before the subset of the first set of bits and the subset of the second set of bits is received by the arithmetic logic unit;
• wherein when the data is allowed to propagate from the first partition circuitry to the second partition circuitry, preshifts by the preshifter are allowed to propagate from the subset of the first set of bits to the subset of the second set of bits, and the arithmetic operation is performed on full word length operands to produce results which are of full word length, the results including a concatenation of the second results and the first results;
• and,
• wherein when the data is prevented from propagating from the first partition circuitry to the second partition circuitry, preshifts by the preshifter are not allowed to propagate from the subset of the first set of bits to the subset of the second set of bits, and the arithmetic operation is performed in parallel operands with bit lengths which are smaller than a bit length of the full word length operands.

A processor which allows parallel data processing, the processor comprising:

• an arithmetic logic unit which performs parallel addition and parallel subtraction, the arithmetic logic unit including
• a plurality of partitions implemented in hardware, each partition for performing a first operation on a set of bits from at least one operand, each of the plurality of partitions having an identical logic structure;
• and,
• a plurality of selection means, each of the plurality of selection means being coupled between two partitions from the plurality of partitions, and each of the plurality of selection means responsive to a selection of operand size to allow and prevent data transfer between the two partitions;
• and,
• a preshifter coupled to an input of the arithmetic logic unit, the preshifter including
• a plurality of shift register partitions, each shift register partition for shifting a set of bits from an operand, and
• at least one selecting means, each of the at least one selecting means being coupled between two shift register partitions from the plurality of shift register partitions, and each of the at least one selecting means responsive to a selection of operand size to allow and prevent shifting of data bits between the two shift register partitions.

A method for providing for parallel data processing within a single processor, the method comprising the steps of:

• (a) performing, by first partition circuitry, an arithmetic operation on a first set of bits from at least one operand to generate first results, including performing a preshift on a subset of the first set of bits;
• (b) performing, by second partition circuitry, the arithmetic operation on a second set of bits from the at least one operand to generate second results, including performing a preshift on a subset of the second set of bits;
• (c) when performing the arithmetic operation on full word length operands allowing data from the first partition circuitry to affect calculation of the second results, results of the addition operation being the concatenation of the second results and the first results;
• and,
• (d) when performing the arithmetic operation in parallel on lit operands, performing the following substep,
• (d.1) preventing data from the first partition circuitry to affect the calculation of the second results, including preventing the preshift on the subset of the first set of bits from propagating across to the subset of the second set of bits;
• wherein step (c) and step (d) are performed utilizing first selection means, coupled between the first partition circuitry and the second partition circuitry, for allowing data to propagate from the first partition circuitry to the second partition circuitry and for preventing data from propagating from the first partition circuitry to the second partition circuitry.