Method and device to authorize access to an instrument comprising a computerized operating system

A method for authorizing access to a protected instrument having a computer-based operating system, a non-cryptographic central processing unit, a memory carrier, a peripheral device, and a program memory having access addresses, the method comprising the steps of:

• providing a first set of buses on which the central processing unit, the memory carrier, and the peripheral device are commonly disposed, the first set of buses including a first address bus, a first data bus, and a first control bus;
• storing data elements at the access addresses in the program memory, the storing step including the step of maintaining the secrecy of the data elements by encoding (1) the data elements and (2) one of the access addresses and the commands used to access the data elements;
• removably inserting a decoding device between the program memory and the memory carrier, the removably inserting step including the step of providing a second set of buses which establish two way communication links between the decoding device and the program memory, the second set of buses including a second address bus, a second data bus, and a second control bus for the program memory;
• and
• limiting access to the data elements stored in the program memory, the limiting step including the steps of
• ascertaining, based on the state of a security logic condition of the decoding device, whether the user of the protected instrument is permitted access to the program memory,
• and, if the user is permitted access, then accessing the program memory from the central processing unit, the accessing step including the steps of
• decoding the encoded data elements by referring to a look-up table,
• decoding the encoded one of the access addresses and the commands by referring to the look-up table, and
• wherein the decoding step is performed by the decoding device, and
• wherein the look-up table is implemented on a single chip,
• and, if the user is not permitted access, then denying the central processing unit access to the encoded data elements and the encoded one of the access addresses and the commands, and wherein the denying step is performed by the decoding device.

A protected instrument requiring access authorization, the protected instrument comprising:

• a non-cryptographic central processing unit;
• a plurality of peripheral devices;
• a program memory, the program memory having data elements stored at access addresses, the data elements being encoded to maintain secrecy of the data elements, and one of the access addresses and the commands used to access the data elements being encoded to maintain the secrecy of the data elements;
• a first male-female connector combination;
• a second male-female connector combination;
• a means for decoding the encoded data elements and the encoded one of the access addresses and the commands,
• the decoding means including a look-up table which is implemented on a single chip and which is used to decode the encoded data elements and the encoded one of the access addresses and the commands,
• wherein, for the decoding of data elements, data elements retrieved from the program memory serve as retrieval addresses for the look-up table, and wherein data elements retrieved from the retrieval addresses of the look-up table represent the data elements retrieved from the program memory in decoded form,
• the decoding means being removably inserted between the program memory and the central processing unit by way of the first male-female connector combination and by way of the second male-female connector combination, the first male-female connector combination removably connecting the decoding means to the central processing unit and the second male-female connector combination removably connecting the decoding means to the program memory, and
• the decoding means having stored therein a security logic condition whose state determines whether the decoding is performed;
• a first set of buses on which the decoding means, the central processing unit, and the plurality of peripheral devices are commonly disposed,
• the first set of buses including a first address bus, a first data bus, and a first control bus, and
• the first address bus, the first data bus, and the first control bus being fed through the first male-female connector combination;
• and
• a second set of buses on which the decoding means and the program memory are commonly disposed,
• the second set of buses establishing two way communication links between the decoding means and the program memory and providing the exclusive communication links between the program memory and the remainder of the protected instrument,
• the second set of buses including a second address bus, a second data bus, and a second control bus for the program memory, and
• the second address bus, the second data bus, and the second control bus being fed through the second male-female connector combination.

A protected instrument comprising:

• a non-cryptographic central processing unit;
• program memory means, the program memory means having data elements stored at access addresses, the data elements being encoded to maintain secrecy of the data elements, and one of the access addresses and the commands used to access the data elements being encoded to maintain the secrecy of the data elements;
• a means for decoding the encoded data elements and the encoded one of the access addresses and the commands,
• the decoding means including a look-up table which is implemented on a single chip and which is used to decode the encoded data elements and the encoded one of the access addresses and the commands,
• the decoding means having stored therein a security logic state which determines whether the decoding is performed, and the decoding means being coupled to the program memory means;
• and
• a memory carrier formed of a connector, the memory carrier being coupled to the program memory means via the decoding means, the memory carrier being coupled to the central processing unit via a set of buses, the set of buses including an address bus, a data bus, and a control bus, and the set of buses being fed through the connector to the decoding means and establishing two way communication links between the central processing unit and the decoding means, the central processing unit and the decoding means being commonly disposed on the first set of buses.