Signal processing delay circuit

A signal recording and reproducing system, comprising:

• a recording medium;
• a sensor for recording a signal on the recording medium or reproducing a signal from the recording medium;
• a signal processing circuit for processing a record signal to the sensor or a reproduction signal therefrom;
• an interface circuit for communicating as data items the processed record and reproduction signals;
• a processor for controlling operation of the system;
• a data acquisition circuit for acquiring data in response to a clock signal synchronized with input data thereto, the data acquisition circuit comprising a window adjustment circuit for achieving a phase adjustment between the data and the clock signal,
• the window adjustment circuit including a signal processing delay circuit including first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal,
• the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means;
• and/or
• a data write circuit for writing data on a recording medium,
• the data write circuit including a write pre-compensation circuit for conducting a positional compensation of data according to a data pattern of the data,
• the write pre-compensation circuit including a signal processing delay circuit including first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal,
• the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.

A signal processing delay circuit configured in a semiconductor integration circuit, comprising:

• a first delay means including a first analog variable delay circuit of which an amount of delay is preset according to a stable reference signal and a phase-locked loop circuit for controlling the preset amount of delay, first delay means producing a delay amount control signal;
• and
• a second delay means including a second analog delay circuit for conducting, according to the delay amount control signal from the first delay means, a fine control operation of an amount of delay for an input signal as an object of processing, wherein
• the first analog variable delay circuit has a circuit configuration substantially identical to that of the second analog variable delay circuit.