Method of and apparatus for phase synchronization with an RDS signal
AssigneeSGS-Thomson Microelectronics S.A.
InventorGerhard Roither
Life of this patent
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Abstract
A method of and an apparatus for phase synchronization of a bit rate clock signal generated in an RDS receiver with a digital RDS signal demodulated on the receiver side, in which both the bit rate clock signal and the RDS signal have the same bit rate. Upon turning on of the RDS receiver and/or switching over of the same to a transmitter receiving frequency different from that received so far, a control signal is generated which, upon occurrence of the next rising edge or, alternatively, of the next falling edge of the RDS signal, effects such a phase angle shift of the bit rate clock signal that the bit rate clock signal, starting from that occurrence, is in phase synchronism with the RDS signal.
Claims23
A method of phase synchronization of a bit rate clock signal generated in an RDS receiver with a digital RDS signal that is demodulated on the receiver side, with the bit rate clock signal and the RDS signal having the same bit rate,
- characterized in that, upon switching on of the RDS receiver and/or upon switching over of the same to a transmitter receiving frequency different from that received so far, a control signal is generated which, upon occurrence of the next rising edge or, alternatively, of the next falling edge of the RDS signal, effects such a phase angle shift of the bit rate clock signal that the bit rate clock signal as of then is in phase synchronism with the RDS signal;
- and
- characterized in that the control signal generated upon switching on and/or over of the RDS receiver is stored temporarily and is released for phase angle shift of the bit rate clock signal by occurrence of the rising or falling edge of the RDS signal.
An apparatus for phase synchronization of a bit rate clock signal generated in an RDS receiver with an RDS signal demodulated on the receiver side, with the bit rate clock signal and the RDS signal having the same bit rate, said apparatus comprising:
- an oscillator on the receiver side producing an oscillator signal, and
- a frequency divider counter having the oscillator signal fed to the input side thereof and delivering at its output the bit rate clock signal,
- characterized in
- that the frequency divider counter comprises a counter resetting input for resetting to an initial count,
- that a control means is provided adapted to generate a control signal upon switching on of the RDS receiver and/or switching over of the same to a different transmitter receiving frequency than that received so far,
- that a temporary storage is provided in which the control signal can be stored temporarily and which has a temporary storage resetting input for canceling the temporary storage contents,
- and in that an edge detector is provided which, upon occurrence of the rising or falling edge of the RDS signal, respectively, issues an edge detection signal causing reading out of the control signal stored in the temporary storage and transfer thereof to the counter resetting input and to the temporary storage resetting input.
A method of phase synchronization of a bit rate clock signal generated in an RDS receiver with a digital RDS signal that is demodulated on the receiver side, with the bit rate clock signal and the RDS signal having the same bit rate, the method comprising the steps of:
- receiving a control signal that is generated upon switching over to a radio frequency different from the radio frequency being received by the RDS receiver;
- temporarily storing the control signal;
- shifting the phase angle of the bit rate clock signal in synchronism with the RDS signal upon occurrence of a transition edge of the RDS signal and when the stored control signal is read;
- and
- removing the temporarily stored control signal.
An apparatus for phase synchronization of a bit rate dock signal generated in an RDS receiver with an RDS signal demodulated on the receiver side, with the bit rate clock signal and the RDS signal having the same bit rate, the apparatus comprising:
- an oscillator;
- a frequency divider having an output, a reset input and a first input connected to the oscillator, the frequency divider generating the bit rate clock signal at its output;
- an edge detector having an input receiving the RDS signal and generating at its output an edge detect signal upon detecting a transition edge of the RDS signal;
- a temporary storage having a first input for receiving a control signal that is indicative of the RDS receiver switching to a radio frequency different from the radio frequency being received, the temporary storage having a reset input and an output;
- and
- a logic circuit having a first input connected to the edge detector output, a second input connected to the temporary storage output, a first output connected to the frequency divider reset input, and a second output connected to the temporary storage reset input, the logic circuit operable to generate at its first and second outputs a reset signal when the edge detector generates the edge detect signal and when the temporarily stored control signal is read.
An RDS radio system comprising:
- an RDS transmitter transmitting an RDS signal;
- and
- an RDS receiver receiving the RDS signal, the RDS receiver including a phase synchronization circuit to synchronize a bit rate clock signal generated in the RDS receiver with the RDS signal demodulated on the receiver side, the bit rate clock signal and the RDS signal having the same bit rate, the phase synchronization circuit including:
- an oscillator;
- a frequency divider having a reset input and a first input connected to the oscillator, the frequency divider generating the bit rate clock signal at its output;
- an edge detector having an input receiving the RDS signal and generating at its output an edge detect signal upon detecting a transition edge of the RDS signal;
- a temporary storage having a first input for receiving a control signal generated upon switching over of the RDS receiver to a radio frequency different from the radio frequency being received, the temporary storage having a reset input and an output;
- and
- a logic circuit having a first input connected to the edge detector output, a second input connected to the temporary storage output, a first output connected to the frequency divider reset input, and a second output connected to the temporary storage reset input, the logic circuit operable to generate at its first and second outputs a reset signal when the edge detector generates the edge detect signal and when the temporarily stored control signal is read.
Dependencies are inferred from the claim text.