US 5,636,227 A · Integrated circuit test mechansim and method

Abstract

An integrated circuit test mechanism based upon the JTAG standard utilises serial scan chains for applying signals to and capturing signals from predetermined nodes within an integrated circuit (2). Multiple independent scan chains (12, 14, 16) are provided for different circuit units (4, 6, 8, 10) within the integrated circuit, i.e. individual scan chains (12, 14) for circuit elements such as a central processing core (4) or a cache memory (8). The scan chain controller (18) is responsive to a scan chain selecting instruction (Scan-N) received at its serial input (20) to capture a scan chain specifying value at the serial input. The scan chain specifying value is then used to control the position of a scan chain multiplexer (28) that selects one of the multiple scan chains to which subsequent instructions received at the serial input are applied.

Claims6

Dependent claims

An integrated circuit comprising:

(i) a plurality of discrete circuit units for performing given functions within said integrated circuit;
(ii) a plurality of serial test scan chains each coupled to a different one of said discrete circuit units;
(iii) a scan chain controller having a serial input for receiving signals from outside of said integrated circuit, said scan chain controller comprising an instruction decoder for decoding a scan chain selecting instruction received at said serial input, and a scan chain register for storing a scan chain specifying value, the scan chain controller being responsive to the decoding of said scan chain selecting instruction by said instruction decoder to cause said scan chain specifying value received at said serial input to be loaded into said scan chain register and to use said scan chain specifying value to control a scan chain multiplexer to connect one of said plurality of serial scan chains to said serial input and upon which further instructions different from said scan chain selecting instruction received at said serial input are to be effected until another scan chain selecting instruction is decoded by said instruction decoder and a corresponding scan chain specifying value loaded into said scan chain register.

Dependencies are inferred from the claim text.

Integrated circuit test mechansim and method

Life of this patent

Integrated circuit test mechansim and method

Life of this patent

Abstract

Claims6