Memory test circuit

A memory test circuit, comprising:

• selection signal generating means for repeatedly outputting a selection signal;
• a first address signal generating circuit which updates a first address signal generated to select a memory cell in a memory in response to said selection signal received from said selection signal generating means;
• a second address signal generating circuit which updates a second address signal generated for selection of said memory cell every time said first address signal generating circuit has finished outputting all kinds of said first address signals once;
• and
• a selector circuit receiving said first and second address signals which said first and second address signal generating circuits generate, for selecting one of said first and second address signals with said selection signal provided from said selection signal generating means and outputting the signal as selected to said memory;
• said first address signal generating circuit including,
• a first linear feedback shift register having a plurality of first registers connected in series, and a first exclusive OR circuit having an output terminal connected to the first register on the first stage in said plurality of first registers, a first input terminal connected to a first feedback path, and a second input terminal, and
• a first NOR gate for executing NOT-OR operation of outputs of all said first registers except the first register on the final stage in said plurality of first registers and outputting its result to said second input terminal of said first exclusive OR circuit.