Technique for jointly performing bit synchronization and error detection in a TDM/TDMA system
AssigneeBell Communications Research, Inc.
InventorsLi-Fung Chang, Robert A. Ziegler
Life of this patent
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Abstract
An improved technique for simultaneously performing bit synchronization and error detection of received digital data bursts in a time division multiplexed/time division multiple access (TDM/TDMA) system, such as that used in conjunction with low power portable digital telephony. With the improved technique both bit synchronization and error detection are performed simultaneously to thereby reduce latency in the transceiver. Since round-trip delay is reduced, echo suppression techniques may not be needed.
Claims52
In a digital wireless communication system, a method for performing bit synchronization and error detection on a data burst containing a received word comprising the steps of:
- reading said data burst containing said received word into a buffer;
- obtaining in parallel from said data burst a plurality of candidate codewords which are positioned with respect to a reference position for said received word;
- obtaining a plurality of error syndromes from each of said plurality of candidate codewords;
- determining from said plurality of error syndromes whether bit errors exist in the candidate codewords, and whether a single candidate codeword falls within a predetermined range of positions;
- and
- where no bit errors are detected and a single candidate codeword for said received word falls within said predetermined range of positions, reading out said received word from a point which corresponds to a proper position.
A method for transmitting an informational bit stream of digital data through a communication channel from a transmitter to a receiver and at said receiver for recovering bit synchronization and performing error detection of a corresponding received bit stream comprising the steps of:
- at the transmitter:
- determining a plurality of parity bits for the informational bit stream;
- generating a first cyclic codeword formed of the informational bit stream and said parity bits;
- inserting first marker bits in said first cyclic codeword so as to form a marked first cyclic codeword;
- and
- transmitting a first burst comprising said marked first cyclic codeword over said channel to said receiver;
- and
- at the receiver:
- receiving a second burst corresponding to said transmitted first burst from said channel, extracting from said second burst a received word corresponding to said marked first cyclic codeword, and reading said received word into a memory;
- obtaining in parallel from said second burst a plurality of candidate codewords which are positioned with respect to a reference position;
- obtaining a plurality of error syndromes from each of said plurality of candidate codewords;
- determining from said plurality of error syndromes whether bit errors exist in the candidate codewords, and whether a single candidate codeword falls within a predetermined range of positions;
- and
- where no bit errors are detected and a single candidate codeword for said received word falls within said predetermined range of positions, reading out said received word from a point which corresponds to a proper position.
An apparatus for performing bit synchronization and error detection on a data burst containing a received word comprising:
- a buffer memory;
- means for reading said data burst containing said received word into said buffer memory;
- means for obtaining in parallel from said data burst a plurality of candidate codewords which are positioned with respect to a reference position for said received word;
- means for obtaining a plurality of error syndromes from each of said plurality of candidate codewords;
- means for determining from said plurality of error syndromes whether bit errors exist in the candidate codewords, and whether a single candidate codeword falls within a predetermined range of positions;
- and
- means for reading out said received word from a point which corresponds to a proper position when no bit errors are detected and when a single position for said received word falls within said predetermined range.
A system for transmitting an informational bit stream of digital data through a communication channel and for recovering bit synchronization and performing error detection of a corresponding received bit stream comprising:
- a transmitter which includes:
- means for determining a plurality of parity bits for the informational bit stream;
- means for generating a first cyclic codeword formed of the informational bit stream and said parity bits;
- means for inserting first marker bits in said first cyclic codeword so as to form a marked first cyclic codeword;
- and
- means for transmitting a first burst comprising said marked first cyclic codeword over said channel to said receiver;
- and
- a receiver which includes:
- a memory;
- means for receiving a second burst corresponding to said transmitted first burst from said channel, extracting from said second burst a received word corresponding to said marked first cyclic word, and reading said received word into said memory;
- means for obtaining in parallel from said second burst a plurality of candidate codewords which are positioned with respect to a reference position;
- means for obtaining a plurality of error syndromes from each of said plurality of candidate codewords;
- means for determining from said plurality of error syndromes whether bit errors exist in the candidate codewords, and whether a single candidate codeword falls within a predetermined range of positions;
- and
- means for reading out said received word from a point in said received word which corresponds to a proper position when no bit errors are detected and a single candidate codeword for said received word falls within said predetermined range of positions.
Dependencies are inferred from the claim text.