Row decoder/driver circuit for determining non selected wordlines and for driving non-selected wordlines to a potential less than the lowest potential of the digit lines
AssigneeMicron Semiconductor, Inc.
InventorLoren L. McLaury
Life of this patent
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Abstract
A semiconductor integrated circuit having a decode circuit for selecting selected and non-selected wordlines and having a driver circuit for driving a potential to the non-selected wordlines which is less than the lowest potential to which any digit lines are driven during the operation of the semiconductor integrated circuit.
Claims15
A row decoder circuit for driving a wordline to a first potential and a second potential, wherein the second potential has a value less than a ground reference potential, and for determining which of said first and second potentials shall be driven to said wordline, the row decoder circuit comprising:
- a) a driver input node for receiving select and non-select signals, the wordline driven to said first potential in response to said select signal and driven to said second potential in response to said non-select signal;
- b) a negative node connectable to a negative potential having a value less than said ground reference potential;
- c) a pull-down device interposed between the wordline and said negative node and responsive to said non-select signal, wherein said second potential is driven to said wordline when said wordline is pulled toward said negative potential through said pull-down device in response to said non-select signal;
- and
- d) a latch circuit coupled to said wordline and said driver input node, said latch circuit configured to selectively latch said wordline to said second potential.
A row decoder circuit for driving a wordline to a first potential and a second potential, wherein the second potential has a value less than a ground reference potential, and for determining which of said first and second potentials shall be driven to said wordline, the row decoder circuit comprising:
- a driver input node for receiving select and non-select signals, the wordline driven to said first potential in response to said select signal and driven to said second potential in response to said non-select signal;
- b) a negative node connectable to a negative potential having a value less than said ground reference potential;
- c) a pull-down device interposed between the wordline and said negative node and responsive to said non-select signal, wherein said second potential is driven to said wordline when said wordline is pulled toward said negative potential through said pull-down device in response to said non-select signal;
- and
- d) a static circuit configured to maintain said select signal at a level capable of driving said wordline to said first potential.
A row decoder circuit for driving a wordline to a first potential and a second potential, wherein the second potential has a value less than a ground reference potential, and for determining which of said first and second potentials shall be driven to said wordline, the row decoder circuit comprising:
- a) a driver input node for receiving select and non-select signals, the wordline driven to said first potential in response to said select signal and driven to said second potential in response to said non-select signal;
- b) a negative node connectable to a negative potential having a value less than said ground reference potential;
- c) a pull-down device interposed between the wordline and said negative node and responsive to said non-select signal wherein said second potential is driven to said wordline when said wordline is pulled toward said negative potential through said pull-down device in response to said non-select signal;
- and
- d) a select signal generator in electrical communication with said driver input node, said select signal generator configured to generate said select signal to have a negative potential less than the ground reference potential.
A circuit having a plurality of memory cells, a plurality of digit lines, and a plurality of wordlines, each one of the memory cells located at an intersection of one of the digit lines and one of the wordlines, comprising:
- a) a means for selecting a non-selected wordline of said plurality of wordlines, said non-selected wordline associated with a non-selected memory cell of said plurality of said memory cells;
- b) a means for driving a potential to the non-selected wordline which is less than a lowest potential driven to any of the digit lines of the plurality during an operation of the circuit;
- and
- c) a latch circuit configured to latch the potential to the non-selected wordline.
A system, comprising:
- a) a circuit having a plurality of memory cells for storing data;
- b) a plurality of digit lines for accepting the data;
- c) a plurality of wordlines, each one of said memory cells located at an intersection of one of said digit lines and one of said wordlines;
- d) a microprocessor for generating an addresses for selecting one of said memory cells for access;
- e) a decode means for selecting a non-selected wordline of said plurality of wordlines in response to the address, said non-selected wordline associated with a non-selected memory cell of said plurality of said memory cells;
- f) a driver means for driving a potential to the non-selected wordline which is less than a lowest potential driven to any of the digit lines of the plurality during an operation of said circuit;
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- g) a latch circuit configured to latch the potential to the non-selected wordline.
A module, comprising:
- a) a plurality of address nodes;
- b) at least one integrated circuit connected to said plurality of address nodes, said integrated circuit comprising
- i) a plurality of memory cells for storing data;
- ii) a plurality of digit lines for accepting the data;
- iii) a plurality of wordlines, each one of said memory cells located at an intersection of one of said digit lines and one of said wordlines;
- and
- iv) a decode means for selecting a non-selected wordline of said plurality of wordlines in response to an address on said plurality of address nodes, said non-selected wordline associated with a non-selected memory cell of said plurality of said memory cells;
- c) a driver means for driving a potential to the non-selected wordline which is less than a lowest potential driven to any of the digit lines of the plurality during an operation of the at least one integrated circuit;
- and
- d) a latch circuit configured to latch the potential to the non-selected wordline.
Dependencies are inferred from the claim text.