Fast cycle time-low latency dynamic random access memories and systems and methods using the same

A memory comprising:

• an array of memory cells arranged in columns, each column associated with a bitline, access to selected cells of said array controlled with a plurality of sets of subwordlines, wherein each subwordline of each set controls ones of said cells coupled to a corresponding group of said bitlines;
• precharge circuitry for precharging a selected said group of bitlines;
• and
• addressing circuitry for selecting a said subwordline controlling said cells coupled to said selected group of bitlines.

A memory subsystem comprising:

• input/output circuitry for inputting and outputting data and addresses;
• and
• at least one memory bank coupled to said input/output circuitry comprising:
• a plurality of columns of memory cells, each cell of a column coupled to a bitline associated with said column and a corresponding one of a plurality of subwordlines;
• precharge circuitry for precharging selected bitlines to a predetermined voltage;
• precharge decoder circuitry for selecting in response to precharge select bits selected bitlines for precharge by said precharge circuitry;
• row decoder circuitry for activating a selected subwordline in response to a received row address to select a set of cells coupled to said selected subwordline for access;
• and
• column decoder circuitry for selecting in response to a column address selected bitlines coupled to selected cells of said set of cells to be accessed.

A method of operating a memory including a plurality of memory cells arranged in columns, the cells of a column coupled to a bitline associated with the column and each cell coupled to a preselected one of a plurality of subwordlines, precharge circuitry for procharging a selected group of bitlines in response to at least one precharge select bit, and addressing circuitry for activating a selected one of the subwordlines in response to an address, the method comprising the steps of:

• during a precharge period, providing at least one precharge select bit for procharging a selected group of bitlines;
• during the precharge period, providing a row address for selecting a subwordline for activation, the subwordline selected for activation controlling cells coupled to the group of bitlines selected for precharge;
• during the precharge period, precharging the selected group of bitlines;
• and
• during an active cycle, accessing at least some of the cells coupled to a subwordline selected for activation during the precharge period.