Auto-precharge during bank selection
AssigneeMicron Technology, Inc.
InventorScott Schaefer
Life of this patent
Estimating the term…
Abstract
A synchronous dynamic random access memory (SDRAM) is responsive to command signals and includes a first bank memory array and a second bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, an active command controlling an active operation on the first bank memory array and to initiate, in a second system clock cycle, a transfer read or write command controlling a read or write transfer operation for transferring data from or to the first bank memory array. The command controller responds to the active command to automatically initiate, in the second system clock cycle, a precharge command controlling a precharge operation on the second bank memory array.
Claims42
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising:
- a first bank memory array having storage cells organized in rows and columns for storing dam;
- a second bank memory array having storage cells organized in rows and columns for storing dam;
- and
- a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a first command controlling a first operation on the first bank memory array and to initiate, at a second active edge of the system clock, a transfer command controlling a transfer operation for transferring dam to or from the first bank memory array, and responsive to the fist command to automatically initiate at the second active edge of the system clock, a third command controlling a third operation on the second bank memory array.
A method of initiating commands in a memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of:
- initiating, at a first active edge of the system clock, in response to selected command signals, a first command controlling a first operation on a first bank memory array;
- initiating, at a second active edge of the system clock, in response to selected command signals, a transfer command controlling a transfer operation for transferring data to or from the first bank memory array;
- and
- automatically initiating, at the second active edge of the system clock, in response to the first command, a third command controlling a third operation on a second bank memory array.
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising:
- a first bank memory array having storage cells organized in rows and columns for storing data;
- a second bank memory array having storage cells organized in rows and columns for storing dam;
- and
- a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, an active command controlling an active operation which includes latching a value representing a row address of the first bank memory array and activating the addressed row of storage cells in the first bank memory array, and responsive to the active command to automatically initiate at a second active edge of the system clock, a precharge command controlling a precharge operation which includes precharging and deactivating the second bank memory array.
A method of initiating commands in a memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of:
- initiating, at a first active edge of the system clock, in response to selected command signals, an active command controlling an active operation;
- performing the active operation which includes the steps of latching a value representing a row address of a first bank memory array and activating the addressed row of storage cells in the first bank memory array;
- initiating, at a second active edge of the system clock, in response to selected command signals, a transfer command controlling a transfer operation for transferring data to or from the first bank memory array;
- and
- automatically initiating, at the second active edge of the system clock, in response to the active command, a responsive to the active command a precharge command controlling a precharge operation;
- and
- performing the precharge operation which includes the steps of precharging and deactivating a second bank memory array.
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising:
- a first bank memory array having storage cells organized in rows and columns for storing data;
- a second bank memory array having storage cells organized in rows and columns for storing data;
- and
- a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a special transfer command controlling a transfer operation for transferring data to or from the first bank memory array, and to automatically initiate at the first active edge of the system clock, a second command controlling a second operation on the second bank memory array.
A method of initiating commands in a synchronous memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of:
- initiating, at a first active edge of the system clock, in response to selected command signals, a special transfer command controlling a transfer operation for transferring data to or from a first bank memory array;
- and
- automatically initiating, at the first active edge of the system clock, in response to the selected command signals, a second command controlling a second operation on a second bank memory array.
Dependencies are inferred from the claim text.