Semiconductor memory device having low power self refresh and burn-in functions

A semiconductor memory device having an oscillator which outputs a preset oscillating clock, and a plurality of row decoders which are selected in response to a combination input of a row address, said semiconductor memory device comprising:

• a first row decoder comprising:
• a first input stage, after being precharged by inputs of a precharge signal and combination signals of a decoded row address, for discharging a first connection node as an output node in response to a first combination input of said decoded row address,
• a first latch circuit arranged between said first connection node and a given second connection node for latching and generating an output signal of said first input stage, and
• a first driver circuit arranged between said second connection node and a first word line for amplifying and generating an output signal of said first latch circuit;
• a second row decoder comprising:
• a second input stage, after being precharged by inputs of the precharge signal and the combination signals of a decoded row address, for discharging a third connection node as an output node in response to a second combination input of said decoded row address,
• a second latch circuit arranged between said third connection node and a given fourth connection node for latching and generating an output signal of said second input stage, and
• a second driver circuit arranged between said fourth connection node and a second word line for amplifying and generating an output signal of said second latch circuit;
• and
• a carry generator arranged between said second connection node and said third connection node for outputting a carry corresponding to a voltage level of said second connection node to said third connection node in response to a control input of an oscillating clock, thereby suppressing power consumption during a self-refresh operation by selecting said second word line using said carry.