Low voltage dynamic memory
AssigneeMicron Technology, Inc.
InventorMirmajid Seyyedy
Life of this patent
Estimating the term…
Abstract
A low voltage high density memory device is described. The memory device uses isolation transistors to adjust the voltage stored on memory cells. The memory device is designed to reduce the differential voltage between memory cells storing different data states. A method is described for reducing leakage current of the memory cells to decrease the need for excessive refresh operations. The memory device is described as operating on a one volt supply and producing a 250 mv digit line swing.
Claims18
An integrated memory circuit comprising:
- a plurality of memory cell capacitors;
- a plurality of access devices connected between the plurality of memory cell capacitors and a communication line, each for selectively connecting one of the plurality of memory cell capacitors to the communication line;
- a sense amplifier circuit;
- and
- an n-type isolation transistor and a p-type isolation transistor electrically located between the sense amplifier circuit and the communication line, the integrated memory circuit is adapted to store a maximum charge on the one of the plurality of memory cells which is less than an upper supply voltage level, and adapted to store a minimum charge on the one of the plurality of memory cells which is greater than a lower supply voltage level.
An integrated memory circuit comprising:
- memory cell capacitors having one plate connected to a source of n-type access transistors, the n-type access transistors having a drain connected to a digit line;
- a sense amplifier circuit;
- and
- an n-type isolation transistor and a p-type isolation transistor electrically located between the sense amplifier circuit and the digit line, the integrated memory circuit is adapted to store a maximum charge on a memory cell which is a p-type transistor threshold voltage less than an upper supply voltage level (Vcc-V.sub.TN), and adapted to store a minimum charge on the memory cell which is a p-type transistor threshold voltage level greater than a lower supply voltage level (Vss+V.sub.TP).
A method of storing data in an integrated memory device, the method comprising the steps of:
- storing a reduced voltage on a first memory capacitor, where the reduced voltage is an n-channel transistor threshold voltage level below a supply voltage;
- and
- storing an increased voltage on a second memory capacitor, where the increased voltage is a p-channel transistor threshold voltage level above a lower reference voltage.
A method of storing data in a memory device, the method comprising the steps of:
- providing a supply voltage to a source and gate of an n-channel transistor, the supply voltage being approximately one volt;
- coupling a drain of the n-channel transistor to a first memory cell, such that the first memory cell is charged to a voltage level which is an n-channel transistor threshold voltage level below the supply voltage;
- connecting a drain and gate of a p-channel transistor to ground;
- and
- coupling a source of the p-channel transistor to a second memory cell, such that the second memory cell is charged to a voltage level which is a p-channel transistor threshold voltage level above the ground.
Dependencies are inferred from the claim text.