Precharge voltage generator

In a semiconductor memory device having a bit line connected to a plurality of memory cell arrays, an improved precharge voltage generator comprising:

• an input node for inputting a control signal in the form of a pulse, said control signal designating the active mode of said semiconductor memory device;
• pulse generation means for generating a pulse signal in response to the control signal from said input node, said pulse signal remaining at a desired logic state for the predetermined time period from the in time point of the active mode of said semiconductor memory device;
• first voltage dividing means for dividing a supply voltage and supplying the divided as a precharge voltage signal to said bit line;
• second voltage dividing means connected in parallel to said first voltage dividing means, said second voltage dividing means being selectively driven in response to the pulse signal from said pulse generation means;
• third voltage dividing means connected in parallel to said first and second voltage dividing means, said third voltage dividing means being driven in the active mode of said semiconductor memory device in response to the control signal from said input node;
• and
• a control current sink means connected in parallel to said first voltage dividing means for increasing an amount of current of the precharge voltage signal to be supplied to said bit line for a predetermined time period from an end time point of an active mode of said semiconductor memory device.