US 5,636,168 AGranted

Method for testing a nonvolatile semiconductor memory device

AssigneeNEC Corporation

InventorKen-Ichi Oyama

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Abstract

A method for testing nonvolatile memory device includes the steps of forming a block including a test row and a first and a second decoding row, by connecting the sources of the memory cells in the test row together to form a common source line, connecting each column of memory cells in the three rows in series, connecting the drains of the memory cells in the second decoding row together to form a common drain line, erasing the memory cells in the first and second decoding rows, successively programming and erasing the memory cells in the test row, and measuring a first drain current flowing through the common drain line with respect to the voltage of the word line of the test row. If the first drain current exhibits a negative threshold voltage, an over-erased memory cell exists in the test row. Thereafter, the total drain current of the memory cell other than the over-erased memory cell and the drain current of the over-erased memory cell can be separately measured for analyzing the tunnel oxide film of the memory cells.

Claims5

Dependent claims

A method for testing a nonvolatile semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in a matrix, each of said memory cells including a transistor having a control gate, a source, a drain and a charge storing layer capable of storing information by accumulating charge thereon, the control gates of the memory cells in each row being connected together to form a word line, said method comprising the steps of:

forming a test block by selecting three rows including a test row and first and second decoding rows from said memory cell array, connecting the sources of the memory cells in said test row together to form a common source line, connecting each of the drains of the memory cells in said test row to a source of a corresponding one of the memory cells in said first decoding row, connecting each of the drains of the memory cells in said first decoding row to a source of a corresponding one of the memory cells in said second decoding row, and connecting the drains of the memory cells in said second decoding row together to form a common drain line;
erasing the memory cells in said first and second decoding rows, and successively programming and erasing the memory cells in said test row;
and
after the steps of said erasing and successively programming and erasing, measuring a first drain current flowing through said common drain line with respect to the voltage of the word line of said test row.

1 more element

Dependencies are inferred from the claim text.