US 5,636,164 A · Gate array for accelerating access to a random access memory

Abstract

An apparatus for rapidly determining a control parameter t=t.sub.0 at which the sum S of n functions F.sub.i (i=1, . . . n) reaches a minimum, a maximum, or a given value, wherein each function F.sub.i (t) changes its first derivative only at given discrete values t.sub.ij of the control parameter t is described. The apparatus has a random access memory (RAM) addressed by the values t.sub.ij, a circuit for summing the second derivatives of the functions, a circuit to perform a double integration to evaluate S, and a comparator to determine the optimum control value; also disclosed is a new gate array (GA) which rapidly reproduces the addresses used to address the RAM while skipping all others. This gate array is advantageously used as a part of the apparatus for determining a control parameter. Further, the use of the devices in a communication network is described.

Claims6

Dependent claims

A gate array for consecutively reproducing all addresses applied to said gate array, comprising:

a first section comprising means to erasably mark each address applied, a first plurality of gates to pass a signal of a lowest marked address while blocking the signals of all other addresses;
a second section comprising a read only memory from which is outputted an address stored in said read only memory activated by the signal of the lowest marked address passed through said first plurality of gates, and a second plurality of gates to erase the marking of the lowest marked address in said first section by applying a pulse of sufficient duration to said second plurality of gates.

Dependencies are inferred from the claim text.

Facts

Application

08/448,083Filed 23 May 1995 · division

Priority

EP 9381021525 Mar 1993

Granted

3 Jun 1997

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H04L 12/2852
Characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]: metropolitan area networks
G06F 17/10
Digital computing or data processing equipment or methods, specially adapted for specific functions: complex mathematical operations
G06Q 10/04
Administration; Management: forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or…
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…

Gate array for accelerating access to a random access memory

Life of this patent

Gate array for accelerating access to a random access memory

Life of this patent

Abstract

Claims6