Loading patent…
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKiyohiro Furutani, Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto, Yoshio Matsuda
Estimating the term…
A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
A semiconductor memory device for reading and writing in normal and test modes, respectively, comprising:
A semiconductor memory device for reading and writing in normal and test modes, respectively, comprising:
A semiconductor memory device for reading and writing in normal and test modes, respectively, comprising:
A semiconductor memory device for reading and writing in normal and test modes, respectively, comprising:
A semiconductor memory device for reading and writing in normal and test modes, respectively, comprising:
A semiconductor memory device for reading and writing in normal and test modes, respectively, comprising:
Dependencies are inferred from the claim text.