US 5,636,162 AGranted

Erase procedure

AssigneeTexas Instruments Incorporated

InventorsTim M. Coffman, Sung-Wei Lin, Phat C. Truong

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Abstract

A procedure for erasing a Flash EPROM array (AR) includes applying a series of erase pulses to all of the subarrays (S1, S2, etc.) of a Flash EPROM array (AR) simultaneously. Between each erase pulse, the memory cells (10) of each sub array (S1, S2, etc.) are simultaneously checked one row at a time and one column position at a time, to see whether or not any cell (10) is over-erased. If, at any time during the procedure a cell (10) is found to be over-erased, the over-erased condition is corrected and the erase procedure continues, but with erase pulses applied only to those subarrays (S1, S2, etc.) having non-erased memory cells (10) as in prior-art subarray erase procedures. Under almost all circumstances, the procedure of this invention decreases over-all erase time.

Claims21

Dependent claims

A procedure for erasing a nonvolatile memory array having at least a first and a second subarray of memory cells, said memory cells in said first subarray being separately flash erasable and said memory cells in said second subarray being separately flash erasable, said procedure comprising:

(a) simultaneously applying at least a flash erase pulse to said first subarray and said second subarray;
(b) testing said memory to determine the depletion condition of any memory cell in said memory, said depletion testing performed by simultaneously checking one column of memory cells per said subarray at a time;
(c) if any memory cell in said memory is depleted, correcting the depletion condition;
(d) testing to determine whether any memory cell in said memory is not erased, said testing performed by simultaneously checking one memory cell per said subarray at a time;
(e) if any memory cell in said first subarray is over-erased and corrected, and if any memory cell in said first subarray is not erased, applying another flash erasing pulse only to said first subarray;
and
(f) if any memory cell in said first subarray is depleted and corrected, and if any memory cell in said second subarray is not erased, applying another flash erasing pulse only to said second subarray.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/664,013Filed 12 Jun 1996
Granted: 3 Jun 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 16/3409
Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells: circuits or methods to…
G11C 16/16
Circuits for erasing electrically, e.g. erase voltage switching circuits: for erasing blocks, e.g. arrays, words, groups
G11C 16/3404
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention: convergence or correction of memory…
G11C 16/3445
Arrangements for verifying correct erasure or for detecting overerased cells: circuits or methods to verify correct erasure of nonvolatile memory…