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US 5,636,161 AGranted
Eprom bit-line interface for implementing programming, verification and testing
AssigneeCypress Semiconductor Corporation
InventorEric N. Mann
Life of this patent
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AssigneeCypress Semiconductor Corporation
InventorEric N. Mann
Estimating the term…
The present invention provides an EPROM bit-line interface with multiple functions. The invention is constructed by combining a bit/sense amplifier with two transparent latches operating on opposite edges of a timing clock. The two transparent latches form a latch and a register for holding the contents of the EPROM during power down. A bit driver is enabled when it is desirable to program the EPROM. The first transparent latch captures the contents of the EPROM when the EPROM is powered down. The first transparent latch also forms the first half of a register for shifting the contents of the EPROM to an external device. The first transparent latch operates on the leading edge of a timing clock. The second transparent latch operates on the trailing edge of a timing clock. By combining two transparent latches in series, a shift register is implemented. The shift register is used to hold the programming information while the EPROM is programmed. The shift register also holds the programming information while the contents of the EPROM are read during verification. The contents of the shift register also appear at the output of the EPROM. This eliminates the need for a multiplexer to select between the output of a shift register or the output of an EPROM during functional testing.
A circuit for implementing programing, verification and testing of a memory array comprising:
A circuit for implementing programming, verification and testing of a memory array comprising:
A circuit for implementing programming, verification and testing of a memory array comprising:
Dependencies are inferred from the claim text.