Nonvolatile semiconductor memory having a stress relaxing voltage applied to erase gate during data write

A non-volatile semiconductor memory, comprising:

• a memory cell array having non-volatile memory cells disposed in a matrix form, each said memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into said floating gate and erased through removal of electrons from said floating gate;
• and
• a memory control circuit coupled to said memory cell array and being driven by a high voltage power source and a low voltage power source, predetermined voltages being applied by said memory control circuit to said control gate, said erase gate and said drain respectively of each said memory cell to enter one of a data write mode, a data erase mode and a data read mode, in said data write mode, high voltages being applied to said control gate and said drain of said memory cell to be data-written, a stress relaxing voltage being applied to each said erase gate of said memory cells not to be data-written, and said stress relaxing voltage being an intermediate voltage between the voltages of said high and low voltage power sources,
• wherein said memory control circuit includes voltage outputting means for outputting said stress relaxing voltage.

A non-volatile semiconductor memory, comprising:

• a memory cell array having non-volatile memory cells disposed in a matrix form, each said memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into said floating gate and erased through removal of electrons from said floating gate;
• and
• a memory control circuit coupled to said memory cell array and being driven by a high voltage power source and a low voltage power source, predetermined voltages being applied by said memory control circuit to said control gate, said erase gate and said drain respectively of each said memory cell to enter one of a data write mode, a data erase mode and a data read mode, in said data write mode, high voltages being applied to said control gate and said drain of said memory cell to be data-written, a stress relaxing voltage being applied to each said erase gate of said memory cells not to be data-written, and said stress relaxing voltage being an intermediate voltage between the voltages of said high and low voltage power sources,
• wherein said stress relaxing voltage reduces a voltage stress causing a possible write error/erase error of each said memory cell not be data-written, and
• wherein said memory control circuit includes voltage outputting means for outputting said stress relaxing voltage.

A non-volatile semiconductor memory, comprising:

• a memory cell array having non-volatile memory cells disposed in a matrix form, each said memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into said floating gate and erased through removal of electrons from said floating gate;
• and
• a memory control circuit coupled to said memory cell array and being driven by a high voltage power source and a low voltage power source, predetermined voltages being applied by said memory control circuit to said control gate, said erase gate and said drain respectively of each said memory cell to enter one of a data write mode, a data erase mode and a data read mode, in said data write mode, high voltages being applied to said control gate and said drain of said memory cell to be data-written, a stress relaxing voltage being applied to each said erase gate of said memory cells not to be data-written, and said stress relaxing voltage being an intermediate voltage between the voltages of said high and low voltage power sources,
• wherein said stress relaxing voltage reduces a voltage stress causing a possible write error/erase error of each said memory cell not be data-written,
• wherein said stress relaxing voltage is generated independently from said high and low voltage power sources, and
• wherein said memory control circuit includes voltage outputting means for outputting said stress relaxing voltage.