Irregular pitch layout for a semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsDaisuke Kato, Yohji Watanabe
Life of this patent
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Abstract
A layout arrangement for a semiconductor memory device provides additional space for locating an additional circuit device in a pitch limited circuit. A space or vacated area is created by laying out a circuit element in a manner in which the pitch of the circuit element and an adjacent circuit element is less than the pitch of two times the pitch of a connecting wire pair in a double-sided layout or less than the pitch of one connecting wire pair.
Claims16
A semiconductor memory device on a semiconductor chip comprising:
- a memory cell array including memory cells arranged in rows and columns;
- bit line pairs connected to said memory cells, each bit line pair consisting of first and second bit lines which are respectively connected to a memory cell in a corresponding one of said columns;
- sense amplifiers coupled to said bit line pairs, each sense amplifier for sensing data on a respective one of said bit line pairs;
- selecting transistors coupled to said bit line pairs for selecting a bit line pair to output complementary data signals onto data lines;
- and
- wherein said selecting transistors and said sense amplifiers are laid out on said semiconductor chip to have a pitch of less than two times a pitch of one of said bit line pairs in a double-sided circuit arrangement.
A layout arrangement for a semiconductor device on a semiconductor chip comprising:
- first line pairs consisting of first and second lines which are respectively connected to a memory cell in one of a corresponding row and corresponding column of a memory cell array;
- sense amplifiers connected to said line pairs, each sense amplifier for sensing data on a respective one of said first line pairs;
- selecting transistors coupled to said line pairs for selecting one of said line pairs to output complementary data signals;
- and
- wherein said selecting transistors and said sense amplifiers are laid out on said semiconductor chip to have a pitch less than a pitch of any of said first line pairs.
A layout arrangement for a semiconductor device comprising:
- m line pairs, wherein m is an integer, each line pair having the same pitch x;
- and
- m sets of circuitry elements, each set corresponding to ones of said m line pairs, said m sets of circuitry elements being laid out within a width of m*x', x' being less than the pitch x;
- and
- a space having a width of m*(x-x').
Dependencies are inferred from the claim text.