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US 5,636,157 AGranted
Modular 64-bit integer adder
AssigneeInternational Business Machines Corporation
InventorsJames H. Hesson, Steven C. Espy
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AssigneeInternational Business Machines Corporation
InventorsJames H. Hesson, Steven C. Espy
Estimating the term…
A high speed, compact low power integer adder unit for advanced microprocessors features modular construction, low gate count and a fast add time. A 64-bit implementation is characterized by a unique combination of dual rail logic circuits and dual carry select path within each of four 16-bit adder building blocks to achieve a one gate delay increment for each additional 16-bit adder building block after the first. Each of the 16-bit adder building blocks are composed of modules that receive four of sixteen bits of the operands, and each of the modules are comprised of submodules. The submodules are in turn comprised of dual rail logic circuits with a dual carry select path so as to constitute a nested carry select architecture wherein the nesting of the dual carry select path extends from submodules to a module and from modules to a basic building block. The dual carry select paths are optimized both internal to the submodules and modules and at the submodule and module boundaries to achieve a minimum gate delay number.
A modular integer adder unit composed of two different basic 16-bit adder building blocks, a first of said two building blocks receiving sixteen least significant bits for each of two operands, there being two or more of a second basic building block receiving remaining operand bits in groups of sixteen, each of said first and second basic building blocks being connected through a carry signal and a complement of the carry signal, said first and second basic building blocks being composed of a plurality of modules and each of said modules in turn being composed of a plurality of submodules, said submodules, modules and basic building blocks being dual rail logic circuits with a dual carry select path so as to constitute a nested carry select architecture wherein the nesting of the dual carry select path extends from submodules to a module and from modules to a basic building block and from basic building blocks to said modular integer adder unit, said modular integer adder unit achieving a one gate delay increment for each additional 16-bit adder building block after the first.
Dependencies are inferred from the claim text.