Arithmetic processor and arithmetic method

An arithmetic processor, comprising:

• a redundant binary multiplication part for generating a plurality of redundant binary partial products and a plurality of supplementary terms from a multiplicand and a recode value of a Booth multiplier relating to a multiplier factor, and for adding the redundant binary partial products and the supplementary terms until the addition results in one redundant binary multiplication result and one supplementary term;
• a path for fetching out a partial product added result on lower digit side which is obtained by adding a plurality of redundant binary partial products generated from a lower digit part of a multiplier factor and a multiplicand in the redundant binary multiplication part;
• and a partial product added result on upper digit side which is obtained by adding a plurality of redundant binary partial products generated from the upper part of the multiplier factor and the multiplicand;
• first, second and third intermediate latches for storing the lower-digit-side and upper-digit-side partial product added results and the finally generated one supplementary term;
• an accumulation result latch;
• a redundant binary accumulation part for accumulating results of the first to third intermediate latches and a value of said accumulation result latch and for storing the thus accumulated result into said accumulation result latch;
• a selector for selecting one of a result of said redundant binary multiplication part and a result of said redundant binary accumulation part;
• and
• a redundant binary/binary conversion part for generating propagations and generations of a redundant binary multiplication result a digit part of which is positioned higher than a digit of the one supplementary term finally generated in the redundant binary multiplication part, based on the value supplied via the selector, and converting the selected result into a binary number, using the thus generated propagations and generations.

An arithmetic method for executing a nonpipeline operation in an arithmetic processor when a multiplication instruction is executed and a pipeline operation when a product-sum operation instruction is executed, said nonpipeline operation comprising the steps of:

• generating a plurality of redundant binary partial products and plurality of supplementary terms from a multiplicand and a recode value of a Booth multiplier relating to a multiplier factor;
• obtaining one pair of redundant binary multiplication results and one supplementary term by adding the redundant binary partial products and the supplementary terms;
• selecting a result by the redundant binary multiplication part;
• generating propagations and generations of the thus selected redundant binary multiplication result, based on the finally generated one supplementary term;
• and
• redundant binary/binary converting the thus selected result of the redundant binary multiplication part by adding the propagations and the generations, and
• said pipeline operation comprising the steps of:
• outputting, in a first stage, a partial product added result on lower digit side obtained by adding a plurality of redundant binary partial products generated from a lower digit part of the multiplier factor and a multiplicand, a partial product added result on upper digit side obtained by adding a plurality of redundant binary partial products generated from an upper digit part of the multiplier factor and the multiplicand, and one supplementary term;
• conducting, in a second stage, a redundant binary addition of the lower-digit-side partial product added result, the upper-digit-side partial product added result, the one supplementary term and a past accumulated value in redundant binary number to obtain a present accumulated result in redundant binary number;
• repeating the multiplication and the accumulation in the respective first and second stages by a number of times specified in the product-sum operation instruction;
• selecting, in a third stage, a redundant binary accumulated result finally obtained after the accumulation at the times specified by the product-sum operation instruction;
• and
• converting the thus selected redundant binary accumulated result into a binary number.

An arithmetic processor for performing multiplication, comprising:

• a redundant binary partial multiplication part for outputting a partial product added result on lower digit side obtained by adding a plurality of redundant binary partial products generated from a multiplicand and a recode value of a Booth multiplier reacting to a lower digit part of a multiplier factor;
• a partial product added result on upper digit side obtained by adding a plurality of redundant binary partial products generated from the multiplicand and a recode value of the Booth multiplier relating to an upper digit of the multiplier factor;
• and a supplementary term of a redundant binary partial product of a most significant digit among the plurality of redundant binary partial products;
• an accumulation part for adding a digit part of the lower-digit-side partial product added result which overlaps digits of the upper-digit-side partial product added result and the upper-digit-side partial product added result;
• a redundant binary/binary partial conversion part for redundant binary/binary converting a digit part of the lower-digit-side partial product added result which does not overlap digits of the upper-digit-side partial product added result;
• a redundant binary/binary conversion part for generating propagations and generations of an accumulated result by the accumulation part based on the supplementary term generated by the binary redundant partial multiplication part, and for redundant binary/binary converting the accumulated result by the accumulation part, using the thus generated propagations and generations.

In an arithmetic processor, a method for executing a multiplication instruction in a nonpipeline operation, comprising the steps of:

• outputting three of:
• a partial product added result on lower digit side obtained by adding a plurality of redundant binary partial products generated from a multiplicand and a recode value of a Booth multiplier reacting to a lower digit part of a multiplier factor;
• a partial product added result on upper digit side obtained by adding a plurality of redundant binary partial products generated from a multiplicand and a recode value of the Booth multiplier relating to an upper digit of the multiplier factor;
• and a supplementary term of a redundant binary partial product of a most significant digit among the plurality of redundant binary partial products;
• adding a digit part of the lower-digit-side partial product added result which overlaps digits of the upper-digit-side partial product added result and the upper-digit-side partial product added result, in parallel with conversion of a digit part of the lower-digit-side partial product added result which does not overlap digits of the upper-digit-side partial product added result from redundant binary number into binary number;
• generating propagations and generations of the thus added result based on the supplementary term of the redundant binary partial product having the most significant digit;
• and
• redundant binary/binary converting the thus generated propagations and generations.

An arithmetic method executed by an arithmetic processor comprising the steps of:

• outputting, in a first stage, three of:
• a lower-digit-side partial product added result obtained by adding a plurality of redundant binary partial products generated from a multiplicand and a recode value of a Booth multiplier relating to a lower digit part of a multiplier factor;
• an upper-digit-side partial product added result obtained by adding a plurality of redundant binary partial products generated from a multiplicand and a recode value of the Booth multiplier relating to an upper digit part of a multiplier factor;
• and a supplementary term of a redundant binary partial product having a most significant digit among the plurality of redundant binary partial products;
• accumulating in redundant binary number, in a second stage, the lower-digit-side partial product added result, the upper-digit-side partial product added result, the supplementary term and a past accumulated value;
• repeating the first and second stages in a pipeline operation;
• redundant binary/binary converting, in a third stage, the added result obtained by a final accumulation in the second stage,
• wherein in the second stage at the final accumulation, a digit part of the lower-digit-side partial product added result which overlaps digits of the upper-digit side partial product added result, the upper-digit-side partial product added result, the supplementary term and the past accumulated value are accumulated by redundant binary number, in parallel with the redundant binary/binary conversion of the digit part of the lower-digit-side partial product added result which does not overlap the digits of the upper-digit-side partial product added result.