PC-controlled direct digital synthesizer and method of operating the same
AssigneeVitaly Buckin
InventorsTheodor Funck, Vitali Buckin
Life of this patent
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Abstract
A direct digital synthesizer (DDS) (1) or digitally operating function generator has one or more channels (A, B, . . . ) each with a phase increment register and is controlled by means of a computer system (2) (e.g. a PC) by the computer system (2) sending bits of information to the DDS.(1). Each of the phase increment registers has a given bit width and in operation at every point in time a stored phase value P. The addition of a phase increment Q of a certain bit length is achieved by specific steps in the method by means of which an overflow is avoided. In control a hardware protocol (4) with a multiplexer ensures that the bits of information sent by the computer system (2) are effective in the DDS (1) either as address bits or as data bits.
Claims20
A method of operating a direct digital synthesizer for generating a frequency, the direct digital synthesizer having one or more channels, with each channel including an n-bit phase increment register for holding a phase increment, and means for incrementing a phase value for generating the frequency, and the direct digital synthesizer having an input for receiving from a computer system n-bit phase increment/decrement values, the method comprising:
- for at least one of the channels, with its phase increment register holding a current increment value P, receiving an increment/decrement value Q;
- and if Q is an increment value, replacing P with P+Q according to the following rule:
- ##EQU2## and if Q is a decrement value, replacing P with P-Q according to the following rule:
- ##EQU3## where *Q is the unary ones complement of Q.
A direct digital synthesizer for generating a frequency, comprising:
- one or more channels, with each channel including an n-bit phase increment register for holding a phase increment and means for incrementing a phase value for generating the frequency;
- an input for receiving from a computer system n-bit phase increment/decrement values, operatively coupled to the incrementing means;
- wherein, for at least one of the channels, with its phase increment register holding a current increment value P, and for a received increment/decrement value Q, the incrementing means is such that
- if Q is an increment value, P is replaced with P+Q according to the following rule:
- ##EQU4## and if Q is a decrement value, P is replaced with P-Q according to the following rule:
- ##EQU5## where *Q is the unary ones complement of Q.
Dependencies are inferred from the claim text.