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US 5,636,142 AGranted
Digital processing circuit comprising test registers
AssigneeSGS-Thomson Microelectronics S.A.
InventorOswald Colavin
Life of this patent
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Abstract
The invention relates to a digital processing circuit comprising a host interface (7) which provides access from the processing circuit's bus (6) to an external data processing system (8). The processing circuit is broken down into blocks (1, 2, 3) with test registers (4, 5) interposed between an upstream block and a downstream block. The test registers (4, 5) are connected to the bus (6) and identified by an address allowing data to be sent to them or read from them.
Claims25
Digital processing circuit comprising:
- a host interface providing access from its bus to an external data processing system;
- said bus comprising control lines, address lines and data lines;
- said processing circuit being broken down into blocks and having test registers interposed between an upstream block and a downstream block;
- wherein each said test register is connected to said lines of the bus, is identified by an address allowing data to be sent to is or the data that it contains to be read, and has an active state, in which it detects transfer orders from the bus, and a rest state, in which it does not;
- each test register comprising means allowing the generation of read or write signals according to the signals present on said lines of the bus making said test registers pass to the active state, and additional means authorizing this write or read operation.
2 more elements
A video image processing circuit comprising:
- a data bus;
- a host interface for connecting said digital processing circuit to an external system bus, said interface connected to said data bus;
- a first video processing block having an input and an output;
- a test register comprising:
- a decoding circuit directly connected to said data bus to monitor and decode the contents of said data bus;
- a logic circuit connected to said decoding circuit;
- a first multiplexer having a first and second input, a control line connected to said decoding circuit, and an output, said second input connected to said data bus;
- a second multiplexer having a first input connected to said output of said first multiplexer, a second input connected to said output of said first processing block, a control line connected to said logic circuit, and an output connected to said first input of said first multiplexer;
- and
- a gate having an input connected to said output of said second multiplexer, an output connected to said data bus, and a control line connected to said decoding circuit.
7 more elements
A video image processing circuit comprising:
- a first bus comprising a control line, an address line and a data line;
- a host interface for connecting said digital processing circuit to an external system bus, said interface connected to said data bus;
- a plurality of video processing blocks each having an image data input and an image data output;
- a plurality of test registers, each connected to said data bus, each of said test registers having a data input and a data output, said data input of each of said test registers connected to said output of an upstream one of said processing blocks, said data output of each of said test registers connected to said input of a downstream one of said processing blocks
- wherein each of said test registers is connected to said control line, said address line and said data line of said first bus.
2 more elements
A video image processing circuit comprising:
- a data bus;
- a host interface for connecting said digital processing circuit to an external system bus, said interface connected to said data bus;
- a first processing block having an input and an output;
- a first test register comprising:
- a decoding circuit directly connected to said data bus to monitor and decode the contents of said data bus;
- a logic circuit connected to said decoding circuit;
- a first multiplexer having a first and second input, a control line connected to said decoding circuit, and an output, said second input connected to said data bus;
- a second multiplexer having a first input connected to said output of said first multiplexer, a second input, a control line connected to said logic circuit, and an output connected to said first input of said first multiplexer and to said input of said processing block;
- and
- a gate having an input connected to said output of said second multiplexer, an output connected to said data bus, and a control line connected to said decoding circuit
- a second test register comprising:
- a decoding circuit directly connected to said data bus to monitor and decode the contents of said data bus;
- a logic circuit connected to said decoding circuit;
- a first multiplexer having a first and second input, a control line connected to said decoding circuit, and an output, said second input connected to said data bus;
- a second multiplexer having a first input connected to said output of said first multiplexer, a second input connected to said output of said first processing block, a control line connected to said logic circuit, and an output connected to said first input of said first multiplexer;
- and
- a gate having an input connected to said output of said second multiplexer, an output connected to said data bus, and a control line connected to said decoding circuit.
14 more elements
A method for testing a video processing block using a testing circuit having an input and an output, wherein said testing circuit is not a video processing block, comprising the steps of:
- connecting an output of a processing block to an input of a first testing circuit;
- accepting and decoding data from a data bus to determine the function desired to be performed by said testing circuit;
- and
- if a write operation is desired, passing a part of said data to on output of said testing circuit;
- if a read operation is desired, passing an input data from said input to said data bus and to said output;
- if a passive state is desired, passing all values at said input directly to said output.
3 more elements
Dependencies are inferred from the claim text.