Method and apparatus for constraining the compaction of components of a circuit layout
AssigneeMentor Graphics Corporation
InventorAjay D. Kamdar
Life of this patent
Estimating the term…
Abstract
Integrated circuit design method and apparatus with user defined constraints for constraining compaction of an integrated circuit layout. Logical boundary constraints allow a user to move layout designs to different process technologies without concern that device size changes will disrupt the layout. Multiple grid constraints allow a user to set grids of different sizes for the same or different circuit layers in a design. And pre-compaction constraints may be imposed by a user to preserve components' relationships in an initial topology throughout the compaction process.
Claims19
A computer-implemented method of constraining compaction of components of a circuit layout, the method comprising the following steps:
- determining constraint reference points for at least two constrained components;
- determining which of the two constrained components has a greatest distance between the components constraint reference point and a specified component edge;
- storing the greatest distance as a logical layout boundary that is offset from a specified physical layout boundary;
- and
- in compacting the constrained components, aligning the reference points of the constrained components with the logical layout boundary to prevent each of the constrained components from extending beyond the physical layout boundary.
A computer-implemented method of constraining components of an circuit layout prior to compaction, the method comprising the following steps:
- storing a pre-compaction constraint for a component;
- storing at least one compaction-only constraint for the circuit layout, said circuit layout including a plurality of components;
- applying the pre-compaction constraint to the component;
- applying said at least one compaction-only constraint to compact the circuit layout;
- and
- maintaining the application of the pre-compaction constraint on the component during compaction of the circuit layout to be consistent with the at least one compaction-only constraint application.
A circuit design apparatus for constraining compaction of components, comprising;
- means for determining constraint reference points for at least two constrained components;
- means for determining which of the two constrained components has a greatest distance between the component's constraint reference point and a specified component edge;
- means for storing the greatest distance as a logical layout boundary offset from a specified physical layout boundary;
- and
- means for aligning the reference points of the constrained components with the logical layout boundary to prevent each of the constrained components from extending beyond the physical layout boundary.
A computer-implemented method of constraining compaction of components of a circuit layout, the method comprising the following steps:
- providing a multiple number of grids as individual constraints for components;
- for each grid constraint, providing a number of grid reference points;
- and
- applying a grid constraint to a component,
- the constrained component thereby constrained according to the individually applied grid.
Dependencies are inferred from the claim text.