US 5,636,130 A · Method of determining signal propagation delay through circuit elements

Abstract

A method is provided for accurately determining the propagation delay of a gate under consideration in a static timing analyzer. This is accomplished by determining both the output load and input rise time of the gate under consideration. These values are then compared with a load versus rise time grid having previously determined values of propagation delay (points) for specified combinations of load and input rise time. These points are then used to interpolate a value of propagation delay for the gate under consideration by an interpolation technique that accounts for at least one of the following non-linear effects: the feed forward capacitance of a gate, soft switching, gate resistance, source and drain resistance, and/or other non-linear effects. The method accounts for each non-linear effect by imparting a corresponding component to propagation delay only in that range of output load and input rise time for which that non-linear effect is most pronounced.

Claims31

Dependent claims

A method of using a computer having a memory to determine a propagation delay associated with a selected gate in a synchronous design which includes clocked elements connected by various paths, each of which may have one or more gates, the selected gate having an associated propagation delay which is defined, at least in part, by a load on the selected gate and an input rise time which is related to the output transition time of a gate immediately preceding the selected gate on a path connecting two clocked elements, the method comprising the following steps:

(a) receiving a grid of points from said memory, each grid point specifying a propagation delay for a unique combination of gate load and input rise time;
(b) determining the load associated with the selected gate;
(c) determining the input rise time for the selected gate;
(d) from the grid, identifying at least three points which specify combinations of gate load and input rise time such that these points surround a point defined by the combination of gate load and input rise time for the selected gate;
and
(e) interpolating within the at least three points identified in step (d) to determine the propagation delay of the selected gate, the interpolating being conducted by a technique that accounts for a non-linear gate effect selected from the group consisting of feedforward capacitance, source and drain resistance, and a slow input rise time.

3 more elements

A computer system for determining the propagation delay of a selected gate in a synchronous design, the selected gate having an associated propagation delay which is defined, at least in part, by a load on the selected gate and an input rise time for the selected gate, the computer system comprising:

a load analyzer which determines associated with the load the selected gate;
an input rise time analyzer which determines the input rise time of the selected gate;
a grid stored in a memory, the grid including a plurality of grid points each having a unique combination of input rise time and load, each grid point also having a value of propagation delay previously determined for a gate having the input rise time and load of that grid point;
and
an interpolator which determines the propagation delay of the selected gate by interpolating within at least four grid points defining a surface of propagation delay values, the surface being shaped such that it accounts for a non-linear gate effect selected from the group consisting of feedforward capacitance, source and drain resistance, and a slow input rise time.

2 more elements

(a) receiving a grid of points from said memory, each grid point specifying a propagation delay for a unique combination of gate load and input rise time;
(b) determining the load associated with the selected gate;
(c) determining the input rise time for the selected gate;
(d) from the grid, identifying at least three points which specify combinations of gate load and input rise time such that these points surround a point defined by the combination of gate load and input rise time for the selected gate;
(e) identifying from among the at least three points surrounding the selected gate's point a closest grid point which is closest to the selected gate point;
(f) specifying outer grid points at least one of which lies beyond the at least three points surrounding the selected gate's point;
(g) with said outer surrounding grid points, determining expected propagation delay values for the closest point using at least two different expressions for propagation delay;
(h) from said expected propagation delay values, identifying which one of the at least two different expressions best predict propagation delay at the closest point;
and
(i) interpolating within the at least three points identified in step (d) to determine the propagation delay of the selected gate, the interpolating being conducted with the expression identified in step (h).

7 more elements

A method of using a computer having a memory to determine an output rise time associated with a selected gate in a synchronous design, the synchronous design including clocked elements connected by various paths, each of which may have one or more gates, the selected gate having an associated output rise time which is defined, at least in part, by a load on the selected gate and an input rise time, the method comprising the following steps:

(a) receiving a grid of points from said memory, each grid point specifying an output rise time for a unique combination of gate load and input rise time;
(b) determining the load associated with the selected gate;
(c) determining the input rise time for the selected gate;
(d) from the grid, identifying at least three points which specify combinations of gate load and input rise time such that these points surround a selected point defined by the combination of gate load and input rise time for the selected gate;
and
(e) interpolating within the at least three points identified in step (d) to determine the output rise time of the selected gate, the interpolating being conducted by a technique that accounts for a non-linear effect selected from the group consisting of feedforward capacitance, gate electrode resistance, source and drain resistance, and a slow input rise time.

3 more elements

Dependencies are inferred from the claim text.

Method of determining signal propagation delay through circuit elements

Life of this patent

Method of determining signal propagation delay through circuit elements

Life of this patent

Abstract

Claims31