Electrical routing through fixed sized module and variable sized channel grids

A computer-implemented method for interconnecting a plurality of adjacent electric circuit modules and channel grid cells having common boundary segments, where the modules have predetermined pluralities of electric connection pins distributed at predetermined locations in a three-dimensional module and have prespecified electrical connections therebetween, and the electric circuit modules are separated by channels of at least a single predetermined width;

• said method comprising:
• constructing a representation of a plurality of electric circuit modules each containing a plurality of pins representing electric terminals of electrical circuitry within the electric circuit module associated with the particular pin,
• dividing the electric circuit modules into module grid cells of predetermined dimensions,
• dividing the channels between the electric circuit modules into variable sized channel grid cells each of which shares common boundary segments with adjacent ones of said module grid cells,
• identifying common boundary segments through which circuit connections can be routed for connection pins having prespecified electrical connections therebetween, so that no more than a single boundary segment on one side of a module grid cell is permitted to serve as a connection path to connection pins of another grid cell,
• selecting first and second electric connection pins for routing an electrical connection path therebetween,
• selecting one of said first and second electric connection pins as the source pin and the other as the target pin and identifying corresponding first and second module grid cells with which the respective target and source pins are associated at target and source module grid cells,
• identifying a first grid cell wavefront of first neighboring grid cells adjacent said source grid cell,
• establishing connection cost values indicative of the burden of making a connection between source and target pins through said first grid cell wavefront at particular ones of the grid cells in said first grid cell wavefront,
• identifying successive grid cell wavefronts of grid cells immediately adjacent the immediately previously established grid cell wave from,
• associating connection cost values with the grid cells in the successive grid cell wavefronts and said first grid cell wavefront indicative of the burdens of establishing a connection between source and target pins through particular ones of the grid cells of said grid cell wavefront, and
• designating a connection route between said source and target pins and through selected grid cells of said grid cell wavefronts in view of said grid cell cost values.

A computer implemented method for routing electrical connections in a semiconductor chip, including:

• defining first and second dimensions of respective selected first and second adjacent electric circuit modules;
• setting a first variable set of relative distance relationships between said first and second adjacent electric circuit modules;
• establishing a variably dimensionable channel grid cell having common boundaries with each of said first and second electric circuit modules;
• and
• defining an electrical connection between said first and second electric circuit modules.

A computer implemented method for routing electrical connections between selected locations in adjacent fixed size electric circuit modules which can be repositioned during routing relative to each other to vary the channel with separating the adjacent electric circuit modules, including:

• defining nodes at comers of each fixed size electric circuit module;
• establishing a variable sized channel cell tangent to each of the adjacent fixed size electric circuit modules;
• and
• routing at least a single electrical connection between said adjacent fixed size electric circuit modules.