Protective circuit for semiconductor power device

A circuit for protection against an increase in output current for an integrated circuit including a power device having a power supply electrode connected to a power supply through an inductive load and a control circuit for switching said power device on and off according to a control circuit input voltage variable between a control circuit deactivation state and a control circuit activation state, the protection circuit comprising:

• a clamping circuit suitable for causing the control circuit to switch the power device off when the maximum current flowing through the power device reaches a preset maximum value, wherein the protection also includes a first circuit means for inhibiting the operation of the clamping circuit for a preset time interval after the power device has been switched on, the time interval lasting at least until the end of a first voltage undershoot on the power supply electrode of the power device caused by the inductive load due to the switching on of the power device, and a second circuit means for keeping the clamping circuit in operation during and after a second voltage undershoot on the power supply electrode caused by the inductive load following the switching off of the power device, wherein said second circuit means comprise a condenser in an N+/P junction located in an epitaxial region contained within an insulation well of the type P in turn contained in an epitaxial layer of the type N-grown on a substrate of the type N+, and an NPN transistor having as the collector an enriched region of the type n+ of said epitaxial region, as the base said insulation well of the type P and as the emitter said epitaxial layer and an underlying substrate, said collector of said NPN transistor being connected by said condenser.