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US 5,635,938 AGranted
Quantizing and dequantizing circuit with reduced size
AssigneeOki Electric Industry Co., Ltd.
InventorEiji Komoto
Life of this patent
Estimating the term…
Abstract
A quantizing and dequantizing circuit has a first memory circuit with integer addresses, in which reciprocal data are stored, and a second memory circuit, in which a quantization table of integers is stored. The Integers stored in the second memory circuit are provided to the first memory circuit as address signals, causing output of the corresponding reciprocal data. Data to be quantized are multiplied by the reciprocal data output by the first memory circuit. Data to be dequantized are multiplied by the integers output from the second memory circuit.
Claims27
A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising:
- a first memory circuit with integer addresses, for storing, at each address, reciprocal data for quantizing said first data, and providing an output of said reciprocal data responsive to the address input, said first memory circuit storing said reciprocal data in a compressed form with leading zero-valued bits removed;
- a second memory circuit for storing a quantization table of integers, and providing output of said integers as said address input to said first memory circuit;
- a multiplier coupled to multiply said second data by the integers output from said second memory circuit, multiply said first data by reciprocals of said integers obtained from the reciprocal data output by said first memory circuit, and provide output of resulting products;
- and
- a zero padder, coupled to add leading zero-valued bits to the output of said first memory circuit in a quantity responsive to the output of said second memory circuit, before said output of said first memory circuit is furnished to said multiplier.
2 more elements
A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising:
- a first memory circuit with integer addresses, for storing, at each address, reciprocal data for quantizing said first data, and providing an output of said reciprocal data responsive to the address input, said first memory circuit storing said reciprocal data in a compressed form with leading zero-valued bits removed and with a single leading one-valued bit removed;
- a second memory circuit for storing a quantization table of integers, and providing an output of said integers as said address input to said first memory circuit;
- a multiplier coupled to multiply said second data by the integers output from said second memory circuit, multiply said first data by reciprocals of said integers obtained from the reciprocal data output by said first memory circuit, and provide output of resulting products;
- and
- a zero padder, coupled to add a single leading one-valued bit to the output of said first memory circuit, then also add leading zero-valued bits in a quantity responsive to the output of said second memory circuit, before said output of said first memory circuit is furnished to said multiplier.
2 more elements
A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising:
- a first memory circuit with integer addresses, for storing, at each address, reciprocal data for quantizing said first data, and providing an output of said reciprocal data responsive to the address input, said first memory circuit storing reciprocal data in a compressed form with leading zeros removed;
- a second memory circuit for storing a quantization table of integers, and providing an output of said integers as said address input to said first memory circuit;
- a multiplier coupled to multiply said second data by the integers output from said second memory circuit, multiply said first data by reciprocals of said integers obtained from the reciprocal data output by said first memory circuit, and provide output of resulting products;
- a first selector controlled by a control signal having a first state indicating quantization and a second state indicating dequantization, coupled to furnish the output of said first memory circuit to said multiplier when said control signal is in said first state, and furnish the output of said second memory circuit to said multiplier when said control signal is in said second state;
- a shifter, coupled to right-shift the output of said multiplier by a number of bits responsive to the output of said second memory circuit, and to output the shifted data;
- and
- a second selector, controlled by said control signal, coupled to select the shifted data output by said shifter when said control signal is in said first state, and to shift the output of said multiplier when said control signal is in said second state.
4 more elements
A method of quantizing first data and dequantizing second data, comprising the steps of:
- storing, in a first memory circuit having integer addresses, reciprocal data for quantizing said first data;
- storing, in a second memory circuit, a quantization table of integers;
- providing the integers stored in said second memory circuit to said first memory circuit as address signals, thereby causing an output of corresponding reciprocal data;
- multiplying said first data by reciprocals of said integers obtained from said reciprocal data, thereby generating quantized data;
- multiplying said second data by the integers output by said second memory circuit, thereby generating dequantized data;
- generating a control signal having a first state indicating quantization and a second state indicating dequantization;
- and
- selecting the output of said first memory circuit or the output of said second memory circuit responsive to said control signal.
5 more elements
A method of quantizing first data and dequantizing second data, comprising the steps of:
- storing, in a first memory circuit having integer addresses, reciprocal data for quantizing said first data, said first memory circuit storing reciprocal data in a compressed form with leading zero-valued bits removed;
- storing, in a second memory circuit, a quantization table of integers;
- providing the integers stored in said second memory circuit to said first memory circuit as address signals, thereby causing an output of corresponding reciprocal data;
- multiplying said first data by reciprocals of said integers obtained from said reciprocal data, thereby generating quantized data;
- multiplying said second data by the integers output by said second memory circuit, thereby generating dequantized data;
- and adding leading zero-valued bits to the output of said first memory circuit in quantities responsive to the integers output by said second memory circuit.
3 more elements
A method of quantizing first data and dequantizing second data, comprising the steps of:
- storing, in a first memory circuit having integer addresses, reciprocal data for quantizing said first data, said first memory circuit storing reciprocal data in a compressed form with leading zero-valued bits removed;
- storing, in a second memory circuit, a quantization table of integers;
- providing the integers stored in said second memory circuit to said first memory circuit as address signals, thereby causing an output of corresponding reciprocal data;
- multiplying said first data by reciprocals of said integers obtained from said reciprocal data, thereby generating quantized data;
- and
- multiplying said second data by the integers output by said second memory circuit, thereby generating dequantized data;
- right-shifting said quantized data by amounts responsive to the integers output by said second memory circuit.
4 more elements
A method of quantizing first data and dequantizing second data, comprising the steps of:
- storing, in a first memory circuit having integer addresses, reciprocal data for quantizing said first data, said first memory circuit storing reciprocal data in a compressed form with leading zero-valued bits removed and with a single leading one-valued bit removed;
- storing, in a second memory circuit, a quantization table of integers;
- providing the integers stored in said second memory circuit to said first memory circuit as address signals, thereby causing an output of corresponding reciprocal data;
- multiplying said first data by reciprocals of said integers obtained from said reciprocal data, thereby generating quantized data;
- multiplying said second data by the integers output by said second memory circuit, thereby generating dequantized data;
- and
- adding a single leading one-valued bit to the output of said first memory circuit.
4 more elements
A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising:
- a first memory circuit storing reciprocal data for quantizing said first data:
- a second memory circuit storing a quantization table of integers for dequantizing said second data;
- a multiplier for multiplying said first data by said reciprocal data and for multiplying said second data by said integers;
- and
- a shifter for shifting an output of said multiplier according to the quantization table of integers.
2 more elements
A quantizing and dequantizing circuit for quantizing first data and dequantizing second data, comprising:
- a first memory circuit storing reciprocal data for quantizing said first data:
- a second memory circuit storing a quantization table of integers for dequantizing said second data;
- a padder for padding the reciprocal data and outputting padded reciprocal data;
- and
- a multiplier for multiplying said first data by said padded reciprocal data and for multiplying said second data by said integers.
2 more elements
Dependencies are inferred from the claim text.