Pipelined multi-stage analog-to-digital converter

A pipelined multi-stage analog-to-digital converter for converting an analog input signal as a sampled and held signal into a digital output signal, said pipelined multi-stage analog-to-digital converter comprising:

• a flash analog-to-digital converter located in each stage, for converting the analog input signal into a digital converted signal;
• a multiplying digital-to-analog converter located in each stage, for converting the digital converted signal into an analog reconstructed signal, obtaining the difference between the analog reconstructed signal and the analog input signal as a residue signal, and transmitting the residue signal to a next stage;
• and
• a digital logic circuit coupled to receive the digital converted signal from said flash analog-to-digital converter of each stage, for converting all received digital converted signals into digital coded values for code error calibration and correction to provide said digital output signal, said digital logic circuit comprising:
• a digital correction logic circuit for correcting non-critical errors between stages;
• a digital calibration logic circuit for calibrating each code error, and for controlling the timing of a calibration sequence and generating memory address signals and control signals;
• an averaging logic circuit for averaging front-end stage errors to produce a mean value;
• a RAM for storing the average code errors;
• and
• a digital subtractor for subtracting stored errors from an uncalibrated digital output of said digital correction logic circuit.

A pipelined multi-stage analog-to-digital converter for converting an analog input signal to a digital output signal, said pipelined multi-stage analog-to-digital converter comprising:

• a sample-and-hold circuit for sampling the analog input signal and providing a sampled analog input signal;
• a first flash analog-to-digital converter coupled to said sample-and-hold circuit, for converting the sampled analog input signal to a first digital output signal;
• a first multiplying digital-to-analog converter coupled to said first flash analog-to-digital converter, for converting said first digital output signal to a first pipelined analog signal and comparing said first pipelined analog signal with said analog input signal to provide a first conversion residue signal representing code errors in said first digital output signal;
• a second flash analog-to-digital converter for converting said first conversion residue signal to a second digital output signal;
• a second multiplying digital-to-analog converter coupled to said second flash analog-to-digital converter, for converting said second digital output signal to a second pipelined analog signal and comparing said second pipelined analog signal with said first conversion residue signal to provide a second conversion residue signal representing code errors in said second digital output signal;
• a third flash analog-to-digital converter for converting said second conversion residue signal to a third digital output signal;
• a third multiplying digital-to-analog converter coupled to said third flash analog-to-digital converter, for converting said third digital output signal to a third pipelined analog signal and comparing said third pipelined analog signal with said second conversion residue signal to provide a third conversion residue signal representing code errors in said third digital output signal;
• a fourth flash analog-to-digital converter for converting said third conversion residue signal to a fourth digital output signal;
• digital correction means for correcting errors in said first, second, third and fourth digital output signals and providing a corrected pipelined digital signal;
• calibration means comprising a memory storing the code errors in said first digital output signal, for calibrating said first digital output signal prior to transmission to said first multiplying digital-to-analog converter and for providing an error digital signal representing stored code errors addressed by said first digital output signal;
• and
• digital subtractor means for digitally subtracting said error digital signal from said corrected pipelined digital signal to provide said digital output signal.

A pipelined multi-stage analog-to-digital converter, comprising:

• a sample-and-hold circuit for successively sampling and holding an analog input signal to be converted to a digital code;
• a plurality of stages coupled in series in a pipeline, a first stage of the pipeline being connected to receive an output of said sample-and-hold circuit and producing a first part of said digital code and a residue voltage, each stage of the pipeline comprising a flash analog-to-digital converter, said flash analog-to-digital converter of each of an intermediate and a final stage converting a residue voltage from a preceding stage to a succeeding part of said digital code, said first stage and said intermediate stage of the pipeline further comprising a multiplying digital-to-analog converter converting a preceding part of said digital code to said residue voltage to a succeeding stage;
• digital correction means for correcting errors in said digital code output from said flash analog-to-digital converter in each stage of the pipeline and providing a corrected pipelined digital code;
• calibration means for calibrating said first part of said digital code and for providing an error digital code;
• and
• digital subtractor means for subtracting said error digital code from said corrected pipelined digital code to provide a digital output code.