Digital read channel utilizing analog-to-digital converter with offset reduction

An analog-to-digital converter (ADC) that converts a differential analog input signal into a sequence of multi-bit digital data characters corresponding to the waveform of the differential analog input signal, the ADC comprising:

• a resistive ladder network that includes a plurality of resisters connected in series to a positive voltage supply, the series-connected resisters having a mid-point voltage level, the series-connected resister being connected to a negative voltage supply via a current source;
• a differential-to-single ended converter that converts the differential analog signal to a corresponding single-ended analog signal, the differential-to-single ended converter including a current gain stage to drive the signal-ended analog signal at an output of the differential-to-single ended converter, wherein the differential-to-single ended converter is responsive to the mid-point voltage level of the resistive ladder network such that the single-ended analog signal has a DC level nominally equal to the mid-point of the resistive ladder network;
• a comparator latch bank that receives a plurality of signals output from the resistive ladder network and the single-ended analog signal and responds to first polarity transition edges of a clock signal by providing a plurality of comparator latch bank output signals;
• an AND latch bank that receives the plurality of comparator latch bank output signals and responds to second polarity transition edges of the clock signal by providing a plurality of AND latch bank output signals;
• an OR latch bank that receives the plurality of AND latch bank output signals and responds to the first polarity transition edges of the clock signal by providing the sequence of multi-bit digital data characters;
• and
• a voltage offset (VOS) reduction circuit that operates in a configuration mode to receive at least a portion of the plurality of output signals from the resistive ladder network and a single-ended analog signal output from the differential-to-single ended converter that corresponds to a zero magnitude differential signal, and to generate a trim current responsive thereto, wherein the VOS reduction circuit also generates the trim current when the ADC is operating in an operating mode
• wherein the gain stage includes means for receiving the trim current and for adjusting the DC level of the single-ended signal in response thereto.

A read channel system for reading digital data stored on a storage element, the read channel system comprising:

• a read head that senses the digital data stored on the storage element and generates a corresponding analog read data signal;
• a pre-amplifier that pre-amplifies the analog read data signal to provide a pre-amplified analog read data signal;
• a first, variable gain, amplifier that receives the pre-amplified analog read data signal as an input and provides an amplified analog read signal as an output;
• an equalizer that shapes transitions of the waveform of the amplified analog read signal to provide an equalized analog read signal;
• an analog-to-digital converter (ADC) that converts tile equalized analog read signal into a sequence of multi-bit digital data characters corresponding to the waveform of the equalized analog read signal, the ADC including
• (i) a resistive ladder network that includes a plurality of resistive elements connected in series to a positive voltage supply, the series-connected resistive elements having a mid-point voltage level and being connected to a negative voltage supply via a current source;
• (ii) a second amplifier including a current gain stage to drive the analog read signal at an output of the second amplifier, wherein the second amplifier is responsive to the mid-point voltage level of the resistive ladder network such that the amplified analog read signal has a DC level equal to the mid-point of the resistive ladder network;
• (iii) a comparator latch bank that receives a plurality of input signals from the resistive ladder network and the amplified analog read signal and responds to first polarity transition edges of a clock signal by providing a plurality of comparator latch bank output signals;
• (iv) a converter circuit that converts the plurality of comparator latch bank output signals into the sequence of multi-bit digital data characters;
• a voltage offset (VOS) reduction circuit that reduces a DC voltage offset of the second amplifier to thereby reduce an error in the digital output of the ADC, the VOS reduction circuit including
• (i) a comparator bank that receives a plurality of input signals from the resistive ladder network and the output of the second amplifier and provides a plurality of comparator bank output signals in response thereto;
• (ii) a latch bank that receives and latches the plurality of comparator bank output signals and provides a plurality of latch bank output signals in response thereto;
• and
• (iii) a current digital to analog converter (IDAC) that provides a current which is a function of the states of the plurality of latch bank output signals;
• and
• (iv) means for providing the current output from the IDAC as a trim current to the gain stage of the second amplifier to thereby reduce a DC voltage offset of the output of the second amplifier;
• and
• a digital signal processor that recovers the digital data from the sequence of multi-bit digital data characters.

An analog-to-digital converter (ADC) that converts an analog input signal into a sequence of multi-bit digital data characters corresponding to the waveform of the analog input signal, the ADC comprising:

• a resistive ladder network that includes a plurality of resisters connected in series to a positive voltage supply, the series-connected resisters having a mid-point voltage level, the series-connected resister being connected to a negative voltage supply via a current source;
• an amplifier that amplifies the analog signal, the amplifier including a current gain stage to drive the analog signal at an output of the amplifier, wherein the amplifier is responsive to the mid-point voltage level of the resistive ladder network such that the amplified signal has a DC level nominally equal to the mid-point of the resistive ladder network;
• a comparator latch bank that receives a plurality of signals output from the resistive ladder network and the amplified analog signal and responds to first polarity transition edges of a clock signal by providing a plurality of comparator latch bank output signals;
• a converter circuit that converts the plurality of comparator latch bank output signals into the sequence of multi-bit digital data characters;
• a voltage offset (VOS) reduction circuit that operates in a configuration mode to receive at least a portion of the plurality of output signals from the resistive ladder network and the amplified analog signal from the amplifier that corresponds to a zero magnitude analog signal, and to generate a trim current responsive thereto, wherein the VOS reduction circuit also generates the trim current when the ADC is operating in an operating mode
• wherein the gain stage includes means for receiving the trim current and for adjusting the DC level of the amplified analog signal in response thereto.