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US 5,635,866 AGranted
Frequency Doubler
AssigneeSGS-Thomson Microelectronics S.A.
InventorsTrevor K. Monk, Andrew M. Hall
Life of this patent
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Abstract
A frequency doubler is described which is capable of receiving four input signals in quadrature and combining them to produce a pair of antiphase output signals at twice the input frequency.
Claims6
A frequency doubler circuit for receiving first to fourth input signals in quadrature and comprising:
- a first set of logic gates comprising a first NOR gate connected to receive the first and second input signals and providing an output therefrom and a second NOR gate connected to receive the third and fourth input signals and providing an output therefrom;
- and
- a second set of logic gates comprising a third NOR gate connected to receive the outputs of the first and second NOR gates and which supplies an output at twice the frequency of the input signals.
A frequency doubler circuit for receiving first to fourth input signals in quadrature and comprising:
- a first set of logic gates having inputs for receiving the input signals and providing outputs therefrom wherein the first set of logic gates comprises a first logic gate connected to receive the first and second input signals, a second logic gate connected to receive the second and third input signals, a third logic gate connected to receive the third and fourth input signals and a fourth logic gate connected to receive the first and fourth input signals;
- and
- a second set of logic gates which have as their inputs only the outputs from the first set of logic gates and which supply as their outputs two signals in antiphase at twice the frequency of the input signals, wherein the second set of logic gates comprises a fifth logic gate connected to receive the outputs of the first and third logic gates and a sixth logic gate connected to receive the outputs of the second and fourth logic gates.
A frequency doubler circuit for receiving first to fourth input signals in quadrature and comprising:
- a first set of logic gates having inputs for receiving the input signals and providing outputs therefrom wherein the first set of logic gates comprises a first NAND gate connected to receive the first and second input signals, a second NAND gate connected to receive the second and third input signals, a third NAND gate connected to receive the third and fourth input signals and a fourth NAND gate connected to receive the first and fourth input signals;
- and
- a second set of logic gates which have as their inputs only the outputs from the first set of logic gates and which supply as their outputs two signals in antiphase at twice the frequency of the input signals, wherein the second set of logic gates comprises a fifth NAND gate connected to receive the outputs of the first and third NAND gates and a sixth NAND gate connected to receive the outputs of the second and fourth NAND gates.
Dependencies are inferred from the claim text.