Programmable phase comparator

A programmable phase comparator comprising:

• a switch circuit having a current source, impedance means, and a transistor circuit connected between the current source and the impedance means, the transistor circuit having first and second inputs for receiving respective first and second input signals having a phase difference, the first input signal including an uninverted first signal and an inverted first signal, and the second input signal including an uninverted second signal and inverted second signal;
• a reference input connected between the transistor circuit and the impedance means for receiving a reference signal having a signal value selectable independently of the first and second input signals, the reference signal including an uninverted reference signal and an inverted reference signal;
• and
• an output connected to the reference input, the output providing an output signal having a component based on the signal value of the reference signal and representing the phase difference of the first and second input signals;
• wherein the transistor circuit comprises:
• a first transistor having a control terminal connected to the first input to receive the uninverted first signal,
• a second transistor having a control terminal connected to the first input to receive the inverted first signal,
• third and fourth transistors, the third transistor having a pair of terminals connected in series with the first transistor and the current source and the fourth transistor having a pair of terminals connected in series with the first transistor and the current source, the third and fourth transistors having respective control terminals coupled to the second input for respectively receiving the uninverted and inverted second signals, and
• fifth and sixth transistors, the fifth transistor having a pair of terminals connected in series with the second transistor and the current source and the sixth transistor having a pair of terminals connected in series with the second transistor and the current source, the fifth and sixth transistors having respective control terminals coupled to the second input for respectively receiving the inverted and uninverted second signals,
• the third and fifth transistors each having one terminal of its respective pair of terminals connected to the reference input to receive the uninverted reference signal and the fourth and sixth transistors each having one terminal of its respective pair of terminals connected to the reference input to receive the inverted reference signal.