High-speed block id encoder circuit using dynamic logic
AssigneeIntel Corporation
InventorsJeffrey M. Abramson, Bryon G. Conley, Borislav Agapiev
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Abstract
A high-speed block id encoder circuit using dynamic logic includes a plurality of input signal lines received from a memory array and a plurality of output signal lines. A first portion of the encoder circuit pre-charges the plurality of output signal lines to a first state. A plurality of transistors coupled together in a single level receives the input signals and discharges the appropriate output signal lines to a second state based on the input signals. The signals produced on the output lines provide an encoded output identifying which one of the plurality of input signal lines is asserted.
Claims14
A high-speed block identifier encoder circuit comprising:
- a plurality of output signal lines for providing an encoded output identifying which one of a plurality of input signals from an array is asserted;
- a first portion coupled to the plurality of output signal lines for pre-charging the plurality of output signal lines to a first state;
- and
- a plurality of transistors coupled together in a single level for receiving the plurality of input signals and for discharging the plurality of output signal lines to a second state based on the plurality of input signals.
A method for generating an encoded block id identifying which one of a plurality of signals input from an array is asserted, the method comprising the steps of:
- (a) receiving a clock signal;
- (b) pre-charging a plurality of output signal lines to a first state when the clock signal is in a second state;
- (c) receiving a first signal of the plurality of input signals after the clock signal transitions to a third state;
- (d) discharging a first set of the plurality of output signal lines to a fourth state in response to the first signal;
- and
- (e) providing the plurality of output signal lines as the encoded block id.
An apparatus for encoding onto a plurality of output signal lines which one of a plurality of signal lines input from an array is asserted, the apparatus comprising:
- a plurality of output signal lines for providing an encoded output identifying which one of the plurality of input signals is asserted;
- a clock signal input line coupled to the plurality of output signal lines through a first plurality of transistors for pre-charging the plurality of output signal lines to a first state;
- a second plurality of transistors coupled together in a first level, wherein a gate terminal of each of the second plurality of transistors is coupled to one of the plurality of input signal lines;
- and
- the second plurality of transistors for discharging the plurality of output signal lines to a second state responsive to the plurality of input signal lines.
An apparatus for generating an encoded block id that identifies which one of a plurality of signals input from a memory array is asserted, the apparatus comprising:
- means for receiving a clock signal;
- means for pre-charging a plurality of output signal lines to a first state when the clock signal is in second first state;
- means for receiving a first signal of the plurality of input signals after the clock signal transitions to a third state;
- means for discharging a first set of the plurality of output signal lines to a fourth state in response to the first signal;
- and
- means for providing the plurality of output signal lines as the encoded block id.
Dependencies are inferred from the claim text.