Overvoltage-tolerant self-biasing CMOS output buffer

An overvoltage-tolerant self-biasing input/output buffer circuit, comprising:

• a first p-channel field effect transistor having a source and a body connected to a first voltage, a gate connected to a first input, and a drain;
• a first n-channel field effect transistor having a source connected to said first input, a body connected to a second voltage, a gate connected to said first voltage, and a drain connected to a first node;
• a second p-channel field effect transistor having a source connected to the drain of said first p-channel transistor, a body connected to a second node;
• a gate connected to said first node, and a drain connected to an output;
• a third p-channel field effect transistor having a source connected to said first node, a body connected to said second node, a gate connected to said first voltage, and a drain connected to said output;
• a second n-channel field effect transistor having a drain connected to said output, a body connected to said second voltage, a gate connected to said first voltage, and a source;
• a third n-channel field effect transistor having a drain connected to the source of said second n-channel field effect transistor, a body and a source connected to said second voltage, and a gate connected to a second input;
• and
• a biasing circuit for biasing said body of said second and said third p-channel field effect transistors, said biasing circuit further comprising:
• a fourth n-channel field effect transistor having a source and a gate connected to said first voltage, a body connected to said second voltage, and a drain connected to said second node;
• and
• a fifth n-channel field effect transistor having a drain connected to said second node, a gate and a source connected to said output, and a body connected to said second voltage.