US 5,635,858 A · Zero-stopping incrementers

Abstract

A zero-stopping incrementer operates on the recognition that half of all digital values that require incrementing will be even numbers; that is, the least significant bit (LSB) is a binary "0". Incrementing such a number merely requires changing the LSB from a binary "0" to a binary "1". For odd numbers (i.e., those where the LSB is a binary "1"), the zero-stopping incrementer searches for the first binary "0" beginning with the LSB. Once found, that binary "0" is changed to a binary "1" and all the binary "1s" preceding it are changed to binary "0s". No change is required to the higher order bits following the first binary "0". This operation is very fast, the worst case being the case when all the binary bits of the number to be incremented are "1s". Nevertheless, the process is significantly increased, especially for 64-bit numbers which are processed by modern superscalar microprocessors. As compared with conventional incrementers using an adder-like scheme, the zero-stopping incrementer is about three times faster with power consumption less than half of the conventional incrementers.

Claims5

Dependent claims

A zero-stopping incrementer comprising:

input means for inputting a binary number to be incremented by one;
an increment control for supplying an increment signal to cause said binary number to be incremented by one;
first logic means for detecting a first logic zero in said binary number beginning with a least significant bit of said binary number;
second logic means for converting said first logic zero to a logic one and converting all bits below said first logic zero, if any, to logic zeros;
and
third logic means for passing all bits of said binary number above said first logic zero.

3 more elements

Dependencies are inferred from the claim text.

Zero-stopping incrementers

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Zero-stopping incrementers

Life of this patent

Abstract

Claims5